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| fedl9445-02 issue date: dec. 20, 2013 ML9445 180-channel lcd driver with built-in ram for lcd dot matrix displays 1/84 general description the ML9445 is an lsi for dot matrix graphic lcd devices carrying out bit map display. this lsi can drive a dot matrix graphic lcd display panel under the control of an 8-bit microcomputer (hereinafter described mpu). since all the functions necessary for driving a bit map type lcd device are incorporated in a single chip, using the ML9445 makes it possible to realize a bit map type dot matrix graphic lcd display system with only a few chips. since the bit map method in which one bit of display ram data turns on or off one dot in the display panel, it is possible to carry out displays with a high degree of freedom such as chinese character displays, etc. with one chip, it is possible to construct a graphic display system with a maximum of 65 180 dots. the ML9445 has 65 common signal outputs and 180 segment signal outputs and one chip can drive a display of up to 65 180 dots. features ? direct display of the ram data using the bit map method display ram data ?1? ... dot is displayed display ram data ?0? ... dot is not displayed (during forward display) ? display ram capacity 65 180 2 = 23,400 bits ? lcd drive circuits 65 common outputs, 180 segment outputs ? mpu interface: can select an 8-bit parallel or serial interface or i 2 c (write only) ? built-in voltage multiplier circuit for the lcd drive power supply ? built-in lcd drive voltage adjustment circuit ? built-in lcd drive bias generator circuit ? can select frame reversal drive or line reversal drive by command ? built-in oscillator circuit (internal rc oscillator/external clock input) ? a variety of commands read/write of display data, display on/off, forwar d/reverse display, all dots on/all dots off, set page address, set display start address, etc. ? power supply voltage logic power supply: v dd -v ss = 2.7 v to 5.5 v voltage multiplier reference voltage: v in -v ss = 2.7 v to 5.5 v (2- to 5-time multiplier available) lcd drive voltage: v bi -v ss = 6.0 to 18.5 v ? package: ML9445dvwa gold bump chip (bump hardness: low, dv) ? this device is not resistant to radiation and light.
fedl9445-02 ML9445 2/84 block diagram v dd v in fr v1 v2 v3 v4 v5 v ss vs1 ? vs2 ? vc3+ vc4+ vc5 + vc6 + vs7- vr v rs irs segment drivers common drivers common output stae selection circuit display data latch circuit display data ram 65 180 2 co lumn a ddress circuit bus ho ld er c8 6 cs1 (sa0) cs2(sa1) a0 rd (e) wr (r/ w ) p/ s res db7(si) db6(scl) db5 db4 db3 db2 db1 db0 oscillator circuit d isplay tim ing g enera tor ccircuit coms coms0 com63 com0 seg179 seg0 line address circuit i/obuffer page address circuit power supply circuit command decoder status mpuinterface sync cl dof m/ s cls coms1 te st3 temperature senso r svd2 vc7+ v h v out1 v out2 vch vc2+ sdaack te st2 te st1 fedl9445-02 ML9445 3/84 absolute maximum ratings v ss = 0 v parameter symbol condition rated value unit applicable pins power supply voltage v dd ta= 25c ?0.3 to +6.5 v v dd bias voltage v bi ta = 25c ?0.3 to +20 v v1 to v5 voltage multiplier output voltage v out ta= 25c ?0.3 to +20 v v out1 ,v out2 voltage multiplier reference voltage v in 2-time multiplication 3-time multiplication 4-time multiplication 5-time multiplication ?0.3 to +5.5 ?0.3 to +5.5 ?0.3 to +5.0 ?0.3 to +4.0 v v in input voltage v i ta = 25c ?0.3 to v dd +0.3 v all inputs output short-circuit current i s ta = 25c 2.0 to +2.0 ma all outputs chip temperature t c ? 125 c ? storage temperature range t stg ? ?55 to +150 c ? note: do not use the ML9445 by short-circuiting one output pin to another output pin as well as to other pin (input pin, input/output pin, or power supply pin). recommended operating conditions v ss = 0 v parameter symbol condition min typ max uni t applicable pins power supply voltage v dd ? 2.7 ? 5.5 v v dd bias voltage v bi ? 6.0 18 18.5 v v1 to v5 voltage multiplier reference voltage v in 2-time multiplication 3-time multiplication 4-time multiplication 5-time multiplication 3.0 2.7 2.7 2.7 ? 5.5 5.5 4.625 3.7 v v in voltage multiplier output voltage v out external input 6.0 18 18.5 v v out1 ,v out2 operating temperature range t a ? ?40 ? 105 c ? note 1: the electrical characteristics are influenced by cog trace resistance. this lsi always has to be evaluated before using. v cc gnd v in v dd v ss v out1 v out2 v2 v5 ML9445 system(mpu) v1 (v bi ) fedl9445-02 ML9445 4/84 note 2: the voltages v dd , v in , v1 to v5, v out1 and v out2 are values taking v ss = 0 v as the reference. note 3: the highest bias potential is v1 and the lowest is v ss . note 4: always maintain the relationship v1 v2 v3 v4 v5 v ss among these voltages. note 5: when using an external power supply, follow the procedure for power application. when applying external power to the v out1 pin only, apply v out1 after v dd. when applying external power to the v out2 pin only, apply v out2 after v dd. when applying external power to the v1 pin only, apply v1 after v dd . when applying external power to the v1 pin to v5 pin, apply v1 to v5 after v dd . note that the above (note 4) must be satisfied including transient state at power application. note 6: when using an external power supply, follow the procedure for power removal described below. when external power is in use for the v out1 pin only, remove v out1 after v dd . when external power is in use for the v out2 pin only, remove v out2 after v dd . when external power is in use for the v1 pin only, remove v1 after v dd . when external power is in use for the v1 pin to v5 pin, remove v1 to v5 after v dd . note that the above (note 4) must be satisfied including transient state at power removal. fedl9445-02 ML9445 5/84 electrical characteristics dc characteristics [v ss =0v, v dd =2.7 to 5.5v, ta =?40 to +105c] parameter symbol condition min typ max unit applicable pins ?h? input voltage v ih 0.8 v dd ? v dd ?l? input voltage v il 0 ? 0.2 v dd v *1 ?h? output voltage v oh i oh = ?0.5 ma 0.8 v dd ? ? ?l? output voltage1 v ol1 i ol = 0.5 ma ? ? 0.2 v dd v *2 ?l? output voltage2 v ol2 i ol = 0.5 ma ? ? 0.2 v dd v sdaack input current 1 i il1 ?1.0 ? +1.0 *3 input current 2 i il2 v i = v dd or v i = 0 v ?3.0 ? +3.0 a *4 input capacitance c i ta=25c, f=10khz ? 8 12 pf *1 v1 output voltage temperature gradient v1tc ta = 25c v1 = 12 v *5 ? -0.06 ? %/c v1 reference voltage v reg ta = 25c 2.925 3.00 3.075 v v rs v1 output voltage v1 *6 10.59 10.86 11.13 v v1 2-time multiplication *7 9 ? ? 3-time multiplication *8 13.5 ? ? 4-time multiplication *9 13.5 ? ? voltage multiplier output voltage v out 5-time multiplication *10 13.5 ? ? v v out1 v out - v1 voltage vot1 *11 0.6 ? ? v v out2, v1 i o = 50 a, v1=10v, 1/9bias ? 1.0 1.5 lcd driver on resistance r on i o = 50 a, v1=6v, 1/4bias ? 2.0 3.0 k seg0 to 179, coms0, coms1, com0 to 63 ta = 25c 799 832 865 khz internal oscillation f osc 666 ? 998 khz *12 oscillator frequency external input f ext ? 100 250 khz cl*12 *1: a0, db0 to db5, db6 (scl), db7 (si), rd (e), wr (r/ w ), cs1 , cs2, cls, cl, m/ s , c86, p/ s , res , irs, fr, dof , sync pins *2: db0 to db7, fr, dof , sync, cl pins *3: a0, rd (e), wr (r/ w ), cs1 , cs2, cls, m/ s , c86, p/ s , res , irs pins *4: applicable to the pins db0 to db5, db6 (scl), db7 (si), cl, fr, dof , sync in the high impedance state. *5: temperature gradient select : (db2, db1, db0)=(0, 1, 0) *6: ta = 25c, d7=0, =57, (1+rb/ra) = 4, voltage multiplier output voltage (v out ) = 13.5 v (external input), lcd drive output = no-load, see power supply circuit. (page 39) fedl9445-02 ML9445 6/84 *7: v in = 5.0 v, voltage multiplier capacitor c1 = 2.6 to 4.0 f, voltage multiplier output load current i = 500 a. only a voltage multiplier circuit operates, not activating the voltage adjustment circuit and v/f circuit, by power control set command. *8: v in = 5.00 v, voltage multiplier capacitor c1 = 2.6 to 4.0 f, voltage multiplier output load current i = 500 a. only a voltage multiplier circuit operates, not activating the voltage adjustment circuit and v/f circuit, by power control set command. *9: v in = 3.75 v, voltage multiplier capacitor c1 = 2.6 to 4.0 f, voltage multiplier output load current i = 500 a. only a voltage multiplier circuit operates, not activating the voltage adjustment circuit and v/f circuit, by power control set command. *10: v in = 3.0 v, voltage multiplier capacitor c1 = 2.6 to 4.0 f, voltage multiplier output load current i = 500 a. only a voltage multiplier circuit operates, not activating the voltage adjustment circuit and v/f circuit, by power control set command. *11: v1 load current i = 400 a. 8 v is externally input to v out2. the voltage adjustment circuit and v/f circuit operate by power control set command. lcd output = no load *12: see table 1 for the relationship between the oscillator frequency and the frame frequency. table 1. relationship among the oscillator frequency (f osc ), external input frequency(f ext ) display clock frequency (f lcdck ), and lcd frame frequency (f fr ) ratio of dividing frequency: 1/n , number of display line : l parameter display clock frequency (f lcdck ) lcd frame frequency (f fr ) 1/65 to 1/50 duty fosc/16/n f osc /(16*n*l) 1/49 to 1/34 duty f osc * (2/3)/16/n f osc *(3/4) /(16*n*l) 1/33 to 1/18 duty f osc *(1/2)/16/n f osc *(1/2) /(16*n*l) when the internal oscillator is used 1/17 or less f osc * (1/4)/16/n f osc *(1/4) /(16*n*l) ML9445 when the internal oscillator is not used f ext /16 f ext /(16*l) fedl9445-02 ML9445 7/84 ? operating current consumption value (1) during display operation, internal power supply off (the current flowing through v dd with v1 to v5 externally applied when an external power supply is used, not including the current for the lcd drive) [v ss =0 v, ta = 25c] rated value display mode symbol condition min typ max unit v dd = 5 v, v1- v ss = 11 v, no load ? 175 300 all-white i dd v dd = 2.7 v, v1- v ss = 8 v, no load ? 155 250 a v dd = 5 v, v1- v ss = 11 v, no load ? 175 300 checker pattern i dd v dd = 2.7 v, v1- v ss = 8 v, no load ? 155 250 a (2) during display operation, internal power supply on (total of currents flowing through v dd and v in ) [v ss =0v, ta=25c] rated value display mode symbol condition min typ max unit frame reversal, v dd, v in = 5 v, 3-time voltage multiplication v1 - v ss = 11 v, no load ? 450 700 frame reversal, v dd, v in = 2.7 v, 4-time voltage multiplication v1 - v ss = 8 v, no load ? 300 600 all-white i ddin 16-line reversal, v dd, v in = 5 v, 3-time voltage multiplication v1 - v ss = 11 v, no load ? 600 800 a frame reversal, v dd, v in = 5 v, 3-time voltage multiplication v1 - v ss = 11 v, no load ? 1450 1700 frame reversal, v dd, v in = 2.7 v, 4-time voltage multiplication v1 - v ss = 8 v, no load ? 1700 2000 checker pattern i ddin 16-line reversal, v dd, v in = 5 v, 3-time voltage multiplication v1 - v ss = 11 v, no load ? 1500 1700 a ? power save mode current consumption [v ss =0v, ta=25c] rated value parameter symbol condition min typ max unit sleep mode i dds1 v dd = 3.7 v ? 4 20 a fedl9445-02 ML9445 8/84 temperature sensor characteristics [v ss =0 v, v dd =2.7 to5.5 v, ta=?40 to+105c] rated value parameter symbol condition min typ max unit output voltage v svd2 -40 25 105 1.482 1.177 0.801 1.506 1.2 0.824 1.529 1.224 0.848 v output voltage temperature gradient v gra ? ? -4.7 ? mv/ output voltage setup time t sen ? 100 ? ? ms operating current i sen 25 ? 10 30 a fedl9445-02 ML9445 9/84 switching characteristics ? system bus write characteristics 1 (80-series mpu) ? system bus read characteristics 1 (80-series mpu) a0 c s 1 (cs2 = ?h?) wr db0 to db7 (write) t aw8 t ds8 t dh8 t cclw t cchw t ah8 t cyc8 v il v ih v il v ih v ih v il v ih v il v ih v il v ih v il v ih a0 c s 1 (cs2 = ?h?) rd db0 to db7 (read) t aw8 t acc8 t cclr t cchr t ah8 t oh8 t cyc8 v il v ih v il v ih v il v ih v il v ih v ih v oh v oh v ol v ol fedl9445-02 ML9445 10/84 [v dd =2.7 to 5.5v, ta=?40 to+105c] rated value parameter symbol condition min max unit address hold time t ah8 5 ? address setup time t aw8 5 ? system cycle time t cyc8 300 ? control l pulse width ( wr ) t cclw 60 ? control l pulse width ( rd ) t cclr 240 ? control h pulse width ( wr ) t cchw 60 ? control h pulse width ( rd ) t cchr 60 ? data setup time t ds8 40 ? data hold time t dh8 15 ? rd access time t acc8 ? 240 output disable time t oh8 cl = 100 pf 10 100 ns note 1: the input signal rise and fall times are specified as 15ns or less. when using the system cycle time for fast speed, the specified values are (tr + tf) (t cyc8 ? t cclw ? t cchw ) or (tr + tf) (t cyc8 ? t cclr ? t cchr ). note 2: all timings are specified taking the levels of 20% and 80% of v dd as the reference. note 3: the values of t cclw and t cclr are specified during the overlapping period of cs1 at ?l? (cs2 = ?h?) and the ?l? levels of wr and rd , respectively. fedl9445-02 ML9445 11/84 ? system bus write characteristics 2 (68-series mpu) ? system bus read characteristics 2 (68-series mpu) a0 c s 1 (cs2 = ?h?) e r/ w db0 to db7 (write) t aw6 t ds6 t dh6 t ewhw t ewlw t ah6 t cyc6 v ih v il v il v il v ih v il v il v il v ih v ih v il v ih v il v ih v il a0 c s 1 (cs2 = ?h?) e db0 to db7 (read) t aw6 t acc6 t ewhr t ewlr t ah6 t oh6 t cyc6 r/ w v il v il v ih v ih v il v ih v il v ih v il v ih v ih v oh v ol v oh v ol fedl9445-02 ML9445 12/84 [v dd =2.7to5.5v, ta=?40 to+105c] rated value parameter symbol condition min max unit address hold time t ah6 5 ? address setup time t aw6 5 ? system cycle time t cyc6 300 ? data setup time t ds6 40 ? data hold time t dh6 15 ? access time t acc6 ? 240 output disable time t oh6 cl = 100 pf 10 100 read t ewhr 240 ? enable h pulse width write t ewhw 60 ? read t ewlr 60 ? enable l pulse width write t ewlw 60 ? ns note 1: the input signal rise and fall times are specified as 15ns or less. when using the system cycle time for fast speed, the specified values are (tr + tf) (t cyc6 ? t ewlw ? t ewhw ) or (tr + tf) (t cyc6 ? t ewlr ? t ewhr ). note 2: all timings are specified taking the levels of 20% and 80% of v dd as the reference. note 3: the values of t ewlw and t ewlr are specified during the overlapping period of cs1 at ?l? (cs2 = ?h?) and the ?h? level of e. fedl9445-02 ML9445 13/84 ? serial interface [v dd =2.7to4.5 v, ta=?40 to+105c] rated value parameter symbol condition min max unit serial clock period t scyc 250 ? scl ?h? pulse width t shw 100 ? scl ?l? pulse width t slw 100 ? address setup time t sas 150 ? address hold time t sah 150 ? data setup time t sds 100 ? data hold time t sdh 100 ? cs setup time t css 150 ? cs hold time t csh 150 ? ns note 1: the input signal rise and fall times are specified as 15ns or less. note 2: all timings are specified taking the levels of 20% and 80% of v dd as the reference. c s 1 (cs2 = ?1?) scl si a0 t css t slw t sds t shw t csh t sas t scyc t sah t sdh t f t r v il v ih v il v il v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih fedl9445-02 ML9445 14/84 ? i 2 c interface timing (v dd = 2.7 to 5.5 v, ta = -40 to +105c) item symbol condition min. max. unit scl clock frequency f scl ? ? 3.4 mhz hold time (repeat) "statrt" condition t hd,sta ? 160 ? scl "l" pulse width t low ? 160 ? scl "h" pulse width t high ? 60 ? setup time for repeat "start" condition t su,sta ? 160 ? data hold time t hd,dat ? 0 70 data setup time t su,dat ? 10 ? setup time for "stop" condition t su,sto ? 160 ? bus free time between "stop" condition and "start" condition t buf ? 160 ? data valid acknowledge time t vd,ack ? ? 240 ns data bus load capacitance cb ? ? 100 pf noise pulse width tolerance t wf ? ? 10 ns note 1: the input signal rise and fall times are specified as 0.1 s or less. note 2: all timings are specified taking the levels of 20% and 80% of v dd as the reference. sda scl sda t buf v ih v ih v il v ih t hd;sta t low v ih v il v il vih t su;sta t high v il t hd;dat t vd;ack t su;dat t su;sto v ih v il v ih v il v ih v il v ih v il v ih v il fedl9445-02 ML9445 15/84 ? display control output timing cl(out) fr t dfr v oh v ih v il [v dd =2.7to5.5v, ta=?40to+105c] rated value parameter symbol condition min typ max unit fr delay time t dfr cl = 50 pf ? 20 80 ns note 1: all timings are specified taking the levels of 20% and 80% of v dd as the reference. note 2: valid only when the device operates in master mode. ? reset input timing [v dd = 2.7 to 5.5 v, ta = ?40 to +105c] rated value parameter symbol condition min typ max unit reset time t r ? ? 1 reset ?l? pulse width t rw1 1 ? ? s noise pulse width tolerance t rw2 ? ? ? 50 ns note 1: the input signal rise and fall times (t r , t f ) are specified as 15 ns or less. note 2: all timings are specified taking the levels of 20% and 80% of v dd as the reference. r es internal state being reset reset complete t rw t r t f t r v ih v il v il v ih fedl9445-02 ML9445 16/84 pin description function pin name number of pins i/o description db0 to db7 2*8 i/o these are 8-bit bi-directional data bus pins that can be connected to 8-bit standard mpu data bus pins. when a serial interface is selected (p/ s = ?l?,c86= ?h?): db7: serial data input pin (si) db6: serial clock input pin (scl) when the serial interface and the i2c interface are selected, db0 to db5 pins will be in the high impedance state. fix the db0 to db5 pins at ?h? or ?l? level. db0 to db7 will be in the high impedance state when the chip select is in the inactive state. a0 2 i normally, the lowest bit of the mpu address bus is connected and used for distinguishing between data and commands. a0 = ?h?: indicates that db0 to db7 is display data. a1 = ?l?: indicates that db0 to db7 is control data. res 2 i initial setting is made by making res = ?l?. the reset operation is made during the active level of the res signal. cs1 (sa0) cs2(sa1) 2*2 i when the parallel interface and the serial interface are selected: these are the chip select signals. the chip select of the lsi becomes active when cs1 is ?l? and also cs2 is ?h? and allows the input/output of data or commands. when the i2c interface is selected: these are the slave address input signals. they set the lower 2 bits of the slave address. rd (e) 2 i the active level of this signal is ?l? when connected to an 80-series mpu. this pin is connected to the rd signal of the 80-series mpu, and the data bus of the ML9445 goes into the output state when this signal is ?l?. the active level of this signal is ?h? when connected to a 68-series mpu. this pin will be the enable and clock input pin when connected to a 68-series mpu. when a serial interface and i 2 c interface are selected (p/ s = ?l?), fix this pin at ?h? or ?l? level. mpu interface wr (r/ w ) 2 i the active level of this signal is ?l? when connected to an 80-series mpu. this pin is connected to the wr signal of the 80-series mpu. the data on the data bus is latched into the ML9445 at the rising edge of the wr signal. when connected to a 68-series mpu, this pin becomes the input pin for the read/write control signal. r/ w = ?h?: read, r/ w = ?l?: write when a serial interface and i 2 c interface are selected (p/ s = ?l?), fix this pin at ?h? or ?l? level. fedl9445-02 ML9445 17/84 function pin name number of pins i/o description c86 2 i this is the pin for selecting the mpu interface type. when parallel interface is selected (p/ s = ?h?): c86 = ?h?: 68-series mpu interface. c86 = ?l?: 80-series mpu interface. when serial interface and i 2 c interface are selected (p/ s = ?l?): c86 = ?h?: serial interface. c86 = ?l?: i 2 c interface. p/ s = ?h?: parallel interface. p/ s = ?l?: serial interface or i 2 c interface. the pins of the lsi have the following functions depending on the state o f p/ s input. p/ s data/command data read/write serial clock ?h? a0 db0 to db7 rd , wr ? ?l? a0 si/sda (db7) ? scl(db6) p/ s 2 i during serial data input, it is not possible to read the display data in the ram mpu interface sdaack 2 i the i 2 c bus acknowledge output signal. normally, use it as it is connected with the sda pin. connect an external pull-up resistor whenever necessary, as it is an open drain pin. the pull-up connection destination supply voltage shall be the v dd supply voltage or less. oscillator circuit cls 2 i this is the pin for selecting whether to enable or disable the internal oscillator circuit for the display clock. cls = ?h?: the internal oscillator circuit is enabled. cls = ?l?: the internal oscillator circuit is disabled (external input). when cls = ?l?, the display clock is input at the pin cl. this is the pin for selecting whether master operation or slave operation i s made towards the ML9445. during slave operation, the synchronization w ith the lcd display system is achieved by inputting the timing signal s necessary for lcd display. m/ s = ?h?: master operation m/ s = ?l?: slave operation the functions of the different circuits and pins will be as follows depending on the states of m/ s and cls signals. m/ s cls oscillator circuit power supply circuit cl fr sync dof ?h? enabled enabled output output output output ?h? ?l? disabled enabled input output output output ?h? disabled disabled input input input input ?l? ?l? disabled disabled input input input input display timing generator circuit m/ s 2 i fedl9445-02 ML9445 18/84 function pin name number of pins i/o description this is the clock input/output pin. the function of this pin will be as follows depending on the states of m/ s and cls signals. m/ s cls cl ?h? output ?h? ?l? input ?h? input ?l? ?l? input cl 2 i/o when the m l9445 is used in the master/slave mode, the corresponding cl pin has to be connected. fr 2 i/o this is the input/output pin for lcd display frame reversal signal. m/ s = ?h?: output m/ s = ?l?: input when the m l9445 is used in the master/slave mode, the corresponding fr pin has to be connected. dof 2 i/o this is the blanking control pin for the lcd display. m/ s = ?h?: output m/ s = ?l?: input when the m l9445 is used in the master/slave mode, the corresponding d of pin has to be connected. display timing generator circuit sync 2 i/o this is the input/output pin for lcd synchronize signal. when the m l9445 is used in the master/slave mode, the corresponding sync pin has to be connected. irs 2 i this is the pin for selecting the resistor for adjusting the voltage v1. irs = ?h?: the internal resistor is used. irs = ?l?: the internal resistor is not used. the voltage v1 is adjusted using the external potential divider resistors connected to the pins vr. t his pin is effective only in the master operation. this pin is tied to the ?h? or the ?l? level during slave operation. v dd 10 ? these pins are tied to the mpu power supply pin v cc . v ss 12 ? these are the 0 v pins connected to the system ground (gnd). vch 3 ? these pins are internal logic power supply pin. connect capacitors between v ss pin. power supply circuit v in 3 ? these are the reference power supply pins of the voltage multiplier circui t f or driving the lcd. fedl9445-02 ML9445 19/84 function pin name number of pins i/o description v rs 2 ? t hese are the output pins for the lcd power supply voltage adjustmen t circuit. leave these pins open. v out1 4 i/o t hese are the output pins during 1 st voltage multiplication. connect a capacitor between these pins and v ss . v h 4 i/o t hese are the power input/output pins during 2 nd voltage multiplication. connect a capacitor between these pins and v ss . v out2 3 i/o t hese are the output pins during 2 nd voltage multiplication. connect a capacitor between these pins and v ss . t hese are the multiple level power supply pins for the lcd powe r supply. the voltages specified for the lcd cells are applied to thes e pins after resistor network voltage division or after impedanc e t ransformation using operational amplifiers. the voltages are specified t aking v ss as the reference, and the following relationship should b e maintained among them. v 1 v2 v3 v4 v5 v ss master operation: when the power supply is on, the following voltage s are applied to v2 to v5 from the built-in power supply circuit. th e selection of voltages is determined by the lcd bias set command. bias 1/4 1/5 1/6 1/7 1/8 1/9 v2 3/4 v1 4/5 v1 5/6 v1 6/7 v1 7/8 v1 8/9 v1 v3 2/4 v1 3/5 v1 4/6 v1 5/7 v1 6/8 v1 7/9 v1 v4 2/4 v1 2/5 v1 2/6 v1 2/7 v1 2/8 v1 2/9 v1 v5 1/4 v1 1/5 v1 1/6 v1 1/7 v1 1/8 v1 1/9 v1 v1 v2 v3 v4 v5 4*5 i/o vr 2 i v oltage adjustment pins. voltages between v1 and v ss are applied using a resistance voltage divider. these pins are effective only when t he internal resistors for voltage v1 adjustment are not used (irs = ?l?). do not use these pins when the internal resistors for voltage v1 adjustment are used (irs = ?h?). vs1? 7 o t hese are the pins for connecting the negative side of the capacitors for 1 st voltage multiplication. connect capacitors between these pins and vc3+, vc5+. vs2? 7 o t hese are the pins for connecting the negative side of the capacitors for 1 st voltage multiplication. connect capacitors between these pins and vc4+, vc6+. vc2+ 5 i t hese are the input pins for 1 st voltage multiplication. t his pin inputs voltage which is open or same with v in depending on v oltage multiplication scaling factor. power supply circuit vc3+ 5 i/o t hese are the input pins for 1 st voltage multiplication. a pply the voltage equal to v in to the pins or leave them open, depending on voltage multiplication values. fedl9445-02 ML9445 20/84 function pin name number of pins i/o description vc4+ 5 i/o t hese are the pins for connecting the positive side of the capacitors fo r 1 st voltage multiplication. connect capacitors between vs2? and thes e pins. for 3-time voltage multiplication, the pins are configured a s inputs for voltage multiplication. vc5+ 5 i/o t hese are the pins for connecting the positive side of the capacitors fo r 1 st voltage multiplication. connect capacitors between vs1? and thes e pins. for 2-time voltage multiplication, the pins are configured as input s f or voltage multiplication. vc6+ 5 o t hese are the pins for connecting the positive side of the capacitors fo r 1 st voltage multiplication. connect capacitors between vs2? and these pins. vs3- 4 o t hese are the pins for connecting the positive side of the capacitors fo r 2 nd voltage multiplication. connect capacitors between vc7+ and these pins. power supply circuit vc7+ 4 o t hese are the pins for connecting the positive side of the capacitors fo r 2 nd voltage multiplication. connect capacitors between vs3- and these pins. t hese are the lcd segment drive outputs. one of the levels among v1, v3, v4, and v ss is selected depending on t he combination of the display ram content and the fr signal output voltage ram data fr forward display reverse display h h v1 v3 h l v ss v4 l h v3 v1 l l v4 v ss power save ? v ss seg0 to seg179 180 o the output voltage is v ss when the display off command is executed. t hese are the lcd common drive outputs. one of the levels among v1, v2, v5, and v ss is selected depending on t he combination of the scan data and the fr signal. scan data fr output voltage h h v ss h l v1 l h v2 l l v5 power save ? v ss lcd drive output com0 to com63 64 o the output voltage is v ss when the display off command is executed. fedl9445-02 ML9445 21/84 function pin name number of pins i/o description lcd drive output coms0 coms1 2 o these are the common output pins only for indicators. both pins output the same signal. leave these pins open when they are not used. the same signal is output in both master and slave operation modes. temp sensor svd2 2 o this is analog voltage output pin for temperature sensor. test1 test3 2*2 i these are the pins for testing the ic chip. it has a internal pull-down resistor. use it as it is connected to gnd. test pin test2 i this pins for testing the ic chip. leave these pins open during normal use. ? dummy 31 ? this is a floating pin. avoid this pin from shorting with pins other than dummy in the wiring on the chip on glass. fedl9445-02 ML9445 22/84 functional description mpu interface ? selection of interface type the ML9445 carries out data transfer using either the 8-bit bi-directional data bus (db0 to db7) or the serial data input line (si/sda). either the 8-bit parallel data input or serial data input can be selected interface as shown in table 2 by setting the p/ s pin and c86 pin to the ?h? or the ?l? level. table 2 selection of interface type (parallel/serial/i 2 c) p/ s c86 cs1 cs2 a0 rd wr db7 db6 db0 to db5 h: parallel input h:68 l:80 cs1 cs1 cs2 cs2 a0 a0 e rd r/ w wr db7 db7 db6 db6 db0 to db5 db0 to db5 l: serial input i 2 c h: serial l:i 2 c cs1 sa0 cs2 sa1 a0 ? ? ? ? ? si sda scl scl ? ? a hyphen (?) indicates that the pin can be tied to the ?h? or the ?l? level. ? parallel interface when the parallel interface is selected, (p/ s = ?h?), it is possible to connect this lsi directly to the mpu bus of either an 80-series mpu or a 68-series mpu as shown in table 3. depending on whether the pin c86 is set to ?h? or ?l?. table 3 selection of mpu during parallel interface (80?/68?series) c86 cs1 cs2 a0 rd wr db0 to db7 h: 68-series mpu bus l: 80-series mpu bus cs1 cs1 cs2 cs2 a0 a0 e rd r/ w wr db0 to db7 db0 to db7 the data bus signals are identified as shown in table 4 below depending on the combination of the signals a0, rd (e), and wr (r/ w ) of table 3. table 4 identification of data bus signals during parallel interface common 68-series 80-series a0 r/ w rd wr display data read display data write status read control data write (command) 1 1 0 0 1 0 1 0 0 1 0 1 1 0 1 0 fedl9445-02 ML9445 23/84 serial interface when the serial interface is selected (p/ s = ?l?, c86 =?h?), the serial data input (si) and the serial clock input (scl) can be accepted if the chip is in the active state ( cs1 = ?l? and cs2 = ?h?). the serial interface consists of an 8-bit shift register and a 3-bit counter. the serial data is read in from the serial data input pin in the sequence db7, db6, ... , db0 at the rising edge of the serial clock input, and is converted into parallel data at the rising edge of the 8th serial clock pulse and processed further. the identification of whether the serial data is display data or command is judged based on the a0 input, and the data is treated as display data when a0 is ?h? and as command when a0 is ?l?. the a0 input is read in and identified at the rising edge of the (8 n) th serial clock pulse after the chip has become active. fig. 1 shows the signal chart of the serial interface. (when the chip is not active, the shift register and the counter are reset to their initial states. no data read out is possible in the case of the serial interface. it is necessary to take sufficient care about wiring termination reflection and external noise in the case of the scl signal. we recommend verification of operation in an actual unit.) fig. 1 signal chart during serial interface ? i 2 c interface when the i 2 c interface is selected (p/ s = ?l?, c86 =?l?), the i 2 c data input (sda) and the i 2 c clock input (scl) can be data input. for the i 2 c interface, each ic is assigned with a 7-bit slave address. the first one byte in the transfer consists of this 7-bit slave address and the r/w b it that indicates the data transfer direction. always input "0" to the eighth r/w bit because the ML9445 is a write-only lsi. the eight bits next to the slave address is a control by te. the first one bit is co: consecutive command setting bit and the next one bit is rs: command/data setting bit (the remaining six bits are the don't care bits). when co = "0": means the last control byte. when co = "1": means the control bytes are successively input. when rs = "0": means the data to be input next is the command data. when rs = "1": means the data to be input next is the display data. the display data can be successively input. r/w s 01 100 sa0 0 a co rs a msb lsb p sa1 c s1 1 db6 2 db5 3 db4 4 db3 5 db2 6 db1 7 db0 8 db7 9 db6 10 db5 11 db4 12 db3 13 db2 14 fedl9445-02 ML9445 24/84 example of data setting ? when inputting two commands ? when inputting the command and display data ? chip select the ML9445 has the two chip select pins cs1 and cs2, and the mpu interface or the serial interface is enabled only when cs1 = ?l? and cs2 = ?h?. when the chip select signals are in the inactive state, the db0 to db7 lines will be in the high impedance state and the inputs a0, rd , and wr will not be effective. when the serial interface has been selected, the shift register and the counter are reset when the chip select signals are in the inactive state. when the i2c interface is selected, cs1 and cs2 become the slave address setting pins sa0 and sa1. ? accessing the display data ram and the internal registers accessing the ML9445 from the mpu side requires merely that the cycle time (t cyc ) be satisfied, and high speed data transfer without requiring any wait time is possible. also, during the data transfer with the mpu, the ML9445 carries out a type of pipeline processing between lsis via a bus holder associated with the internal data bus. for example, when the mpu writes data in the display data ram, the data is temporarily stored in the bus holder, and is then written into the display data ram before the next data read cycle. further, when the mpu reads out data in the display data ram, first a dummy data read cycle is carried out to temporarily store the data in the bus holder which is then placed on the system bus and is read out during the next read cycle. there is a restriction on the read sequence of the display data ram, which is that the read instruction immediately after setting the address does not read out the data of that address, but that data is output as the data of the address specified during the second data read sequence, and hence care should be taken about this during reading. therefore, always one dummy read is necessary immediately after setting the address or after a write cycle: (the status read cannot use dummy read cycles.) this relationship is shown in figs 2(a) and 2(b). s 01 100 sa1 0 a 10 aa 01 aaa aaap display data display data command display data display data 0 when inputting two commands s 01 100 1 sa0 0 a 10 aa 00 aap command data/com command v ih fedl9445-02 ML9445 25/84 ? data write fig. 2(a) write sequence of display data ram ? data read fig. 2(b) read sequence of display data ram dn = data n = address data data bus holder dn latch dn + 1 w r mpu write signal internal timing dn + 2 dn + 3 dn dn + 1 dn + 2 dn + 3 data column address read signal address preset n unknown dn dn + 1 preset n unknown dn dn + 1 dn + 2 increment n + 1 n + 2 r d mpu w r bus holder internal timing address set n data read (dummy) data read dn data read dn + 1 fedl9445-02 ML9445 26/84 display data ram ? display data ram this is the ram storing the dot data for display and has an organization of 65 (8 pages 8 bits +1) 180 2 bits. it is possible to access any required bit by specifying the page address and the column address. since the display data db7 to db0 from the mpu corresponds to the lcd display in the direction of the common lines as shown in fig. 3, there are fewer restrictions during display data transfer when the ML9445 is used in a multiple chip configuration, thereby making it easily possible to realize a display with a high degree of freedom. also, since the display data ram read/write from the mpu side is carried out via an i/o buffer, it is done independent of the signal read operation for the lcd drive. consequently, the display is not affected by flickering, etc., even when the display data ram is accessed asynchronously during the lcd display operation. db0 0 1 1 1 0 com0 db1 1 0 0 0 0 com1 db2 0 0 0 0 0 com2 db3 0 1 1 1 0 com3 db4 1 0 0 0 0 com4 display data ram lcd display fig. 3 relationship between display data ram and lcd display ? page address circuit / column address circuit the page address of the display data ram is specified using the page address set command as shown in fig. 4. for address incremental direction, either th e column direction or page direction can be selected by the display data input direction select command. whichever direction is ch osen, increment is carried out by positive one(+1) after write or read operation. when the column direction is selected for address incremen t, the column address is increased by +1 for every write or read operation. after the column address has accessed up to b3h, the page address is incremented by +1 and the column address shifts to 00h. when the page direction is selected for address increment, the page address is increased with the column address locked in position. when the page address has accessed up to page17, the column address is incremented by +1, and the page address goes to page 0. whichever direction is selected for address increment, the page address goes back to page 0 and column address to 00h after access up to the column address b3h of page address page17. also, as is shown in table 5, it is possible to reve rse the correspondence relationship between the display data ram column address and the segment output using the adc command (the segment driver direction select command). this reduces the ic placement restrictions at the time of assembling lcd modules. table 5 correspondence relationship between the display data ram column address and the segment output segment output adc seg0 seg179 db0 = ?0? 00(h) column address b3(h) db0 = ?1? b3(h) column address 00(h) fedl9445-02 ML9445 27/84 ? line address circuit the line address circuit is used for specifying the lin e address corresponding to the common output when displaying the contents of the display data ram as is shown in fig. 4. normally, the topmost line in the display is specified using the display start line address set command (com0 output in the forward display state of the common output, and com63 output in the reverse display state). the display area starts from the specified display start line address to cover the area co rresponding to the lines specified by the duty set command in the direction where the line address increments. it is possible to carry out screen scrolling by dynamically changing the line address using the display start line address set command. ? display data latch circuit the display data latch circuit is a latch for temporarily storing the data from the display data ram before being output to the lcd drive circuits. since the commands for selecting forward/reverse display and turning the display on/off control the data in this latch, the data in the display data ram will not be changed. oscillator circuit this is an rc oscillator that generates the display clock. the oscillator circuit is effective only when m/ s = ?h? and also cls = ?h?. the oscillations will be stopped when cls = ?l?, and the display clock has to be input to the cl pin. fedl9445-02 ML9445 28/84 fig. 4 display data ram address map page address data line com db4 db3 db2 db1 db0 address output db0 00 ( h ) com0 db1 01 ( h ) com1 db2 02 ( h ) com2 db3 03 ( h ) com3 db4 04 ( h ) com4 db5 05 ( h ) com5 db6 06 ( h ) com6 db7 07 ( h ) com7 db0 08 ( h ) com8 db1 09 ( h ) com9 db2 0a ( h ) com10 db3 0b ( h ) com11 db4 0c ( h ) com12 db5 0d ( h ) com13 db6 0e ( h ) ( start ) com14 db7 db0 db1 31 ( h ) com49 db2 32 ( h ) com50 db3 33 ( h ) com51 db4 34 ( h ) com52 db5 35(h) com53 db6 36 ( h ) com54 db7 37(h) com55 db0 38 ( h ) com56 db1 39(h) com57 db2 3a ( h ) com58 db3 3b (h) com59 db4 3c ( h ) com60 db5 3d (h) com61 db6 3e ( h ) com62 db7 3f(h) com63 db0 40 ( h ) db1 41(h) db2 42 ( h ) db3 43(h) db4 44 ( h ) db5 45 ( h ) db6 46 ( h ) db7 47 ( h ) db0 48 ( h ) db1 49 ( h ) db2 4a ( h ) db3 4b ( h ) db4 4c ( h ) db5 4d ( h ) db6 4e ( h ) db7 db0 db1 71 ( h ) db2 72 ( h ) db3 73 ( h ) db4 74 ( h ) db5 75 ( h ) db6 76 ( h ) db7 77 ( h ) db0 78 ( h ) db1 79 ( h ) db2 7a ( h ) db3 7b ( h ) db4 7c ( h ) db5 7d ( h ) db6 7e ( h ) db7 7f ( h ) 10 00 0db0 pa g e16 80 ( h ) coms 10 00 1db0 pa g e17 81 ( h ) 00(h) 01(h ) 02(h) 03(h) 04(h) 05(h) 06(h ) 07(h) af(h) b0(h) b1(h) b2(h) b3(h) 0 db 0 adc column address b3(h) b2(h) b1(h) b0(h) af(h) ae(h) ad(h) ac(h) 04(h) 03(h) 02(h) 01(h) 00(h) 1 db 0 seg0 seg1 seg2 seg3 seg4 seg5 se g 6 seg7 seg175 seg176 seg177 seg178 seg179 lcd output when the common output state is normal display page14 page15 mx page0 page1 page6 page7 mx 01 1 1 1 0 01 11 00 11 0 00 10 00 1 1 1 00 0 11 1 00 00 00 0 0 0 mx mx mx mx mx 64line 0page8 page9 the 80(h) is displayed irrespective of the display start line address. fedl9445-02 ML9445 29/84 display timing generator circuit this circuit generates the timing signals for the line address circuit and the display data latch circuit from the display clock. the display data is latched in the display data latch circuit and is output to the segment drive output pins in synchronization with the display clock. this circuit generates the timing signals for the line address circuit and the display data latch circuit from the display clock. the display data is latched in the display data latch circuit and is output to the segment drive output pins in synchronization with the display clock. the read out of the display data to the lcd drive circuits is completely independent of the display data ram access from the mpu. as a result, there is no bad influence such as flickering on the display even when the display data ram is accessed asynchronously during the lcd display. also, the intern al common timing and lcd frame reversal (fr), field start signal (sync) are generated by this circuit from the display clock. the drive waveforms of the frame reversal drive method shown in fig. 5(a) for the lcd drive circuits are generated by this circuit. the drive waveforms of the line reversal drive method shown in fig. 5(b) are also generated by the command. ram data v ss v5 com1 64 65 1 2 3 4 5 6 v2 v1 v ss v4 segn v3 v1 60 61 62 63 64 65 1 23 4 5 6 v ss v5 com0 v2 v1 fr lcdck (display clock) fig. 5(a) waveforms in the frame reversal drive method fedl9445-02 ML9445 30/84 ram data v ss v5 com1 v2 v1 v ss v4 segn v3 v1 v ss v5 com0 v2 v1 64 1 2 3 4 5 6 60 61 62 63 64 65 1 2 3 4 5 6 lcdck (display clock) f r 65 fig. 5(b) waveforms in the line reversal drive method when the ML9445 is used in a multiple chip configuration, it is necessary to supply the slave side display timing signals (fr, cl, and dof ) from the master side. the statuses of the signals fr, cl, and dof are shown in table 6. table 6 display timing signals in master mode and slave mode operating mode fr cl dof sync internal oscillator circuit enabled (cls = h) output output output output master mode (m/ s = ?h?) internal oscillator circuit disabled (cls = l) output input output output internal oscillator circuit disabled (cls = h) input input input input slave mode (m/ s = ?l?) internal oscillator circuit disabled (cls = l) input input input input fedl9445-02 ML9445 31/84 common output state selection circuit (see table 7) since the common output scanning directions can be set using the common output state selection command in the ML9445, it is possible to reduce the ic placement restrictions at the time of assembling lcd modules. table 7 common output state settings state common scanning direction forward display com0 com63 reverse display com63 com0 lcd drive circuit this lsi incorporates 246 sets of multiplexers for the ML9445 that generate 4-level outputs for driving the lcd. these output the lcd drive voltage in accordance with the combination of the display data, common scanning signals, and the fr signal. fig. 6 shows examples of the segment and common output waveforms in the frame reversal drive method. fedl9445-02 ML9445 32/84 fig. 6 output waveforms in the frame reversal drive method (fr waveform/common waveform/segment waveform/voltage difference between common and segment) com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 fr com0 com1 com2 seg0 seg1 seg2 com0-seg0 com0-seg1 v dd v ss v1 v2 v3 v4 v5 v ss v1 v2 v3 v4 v5 v ss v1 v2 v3 v4 v5 v ss v1 v2 v3 v4 v5 v ss v1 v2 v3 v4 v5 v ss v1 v2 v3 v4 v5 v ss v1 v2 v3 v4 v5 0v -v5 -v4 -v3 -v2 -v1 v1 v2 v3 v4 v5 0v -v5 -v4 -v3 -v2 -v1 seg0 seg1 seg2 seg3 seg4 fedl9445-02 ML9445 33/84 power supply circuit the ML9445 includes a power supply circuit for generating the voltage required for driving liquid crystals, consisting of four blocks; the 1 st voltage multiplier circuit, 2 nd voltage multiplier circuit, v1 voltage adjustment circuit, and voltage follower circuit. the circuit is effective only when the master operates. in the power supply circuit, it is possible to control the on/off of each of the circuits of the 1 st voltage multiplier circuit, 2 nd voltage multipliers circuit, v1 voltage adjustment circuit, and voltage follower circuit separately, by using the power control set command. as a result, it is possible to use some parts of functions of both the external power supply and the internal power supply. table 8-1 describes the functions controlled by the 4-bit data of the power control set command and table 8-2 outlines the functions of power supply blocks. figure 6-2 shows the voltage relationship among the power supply circuit blocks. table 8-1 details of functions controlled by the bits of the power control set command control bit function controlled by the bit db3 2 nd voltage multiplier circuit control bit db2 1 st voltage multiplier circuit control bit db1 voltage adjustment circuit (v1 voltage adjustment circuit) control bit db0 voltage follower circuit (v/f circuit) control bit v ss v in v out1 vh v out2 x2 v 1 v 2 v 3 v 4 v 5 1 st voltage x2 x5 multiplier circuit 2 nd voltage multiplier circuit v1 voltage adjustment circuit v/f circuit fig. 6-2 the voltage relationship among the power supply circuit blocks. fedl9445-02 ML9445 34/84 table 8-2 overview of power supply block functions parameter function input voltage output voltage 1 st voltage multiplier circuit generates a multiplied voltage vout1 by multiplying the voltage between vin and gnd using the charge pump. connecting a capacitor for voltage multiplication allows you to multiply the voltage by 2 to 5 times. v in v out1 2 nd voltage multiplier circuit consists of a voltage adjustment circuit and a 2-time voltage multiplier circuit. the voltage adjustment circuit generates vrs as the base voltage of the 2-time voltage multiplier circuit, and then the 2-time voltage multiplier circuit generates vout2 by multiplying vrs by 2 times. v out1 vh, v out2 v1 voltage adjustment circuit this circuit adjusts the v1 voltage and generates the lcd drive voltage v1. v out2 v1 voltage follower circuit resistive division is performed between v1 and vss with a specified bias ratio, and the lcd drive voltages v2, v3, v4, and v5 are generated by the voltage follower. v1 v2, v3, v4, v5 for the combination of power supply circuit operations, the six possible states shown in table 9 can be set by the register value of the power control set command. table 9 sample combination for reference circuit no. state used db3 db2 db1 db0 2 nd voltage multiplier 1 st voltage multiplier v1 adjustment v/f external voltage input 1 only the internal power supply is used 1 1 1 1 on on on on v in 2 only the internal power supply is used (2 nd voltage multiplier is not used) 0 1 1 1 off on on on v in 3 only the internal power supply is used (1 st voltage multiplier is not used) 1 0 1 1 on off on on v out1 4 v1 adjustment and v/f circuits are used 0 0 1 1 off off on on v out2 5 only v/f circuits are used 0 0 0 1 off off off on v1 6 only the external power supply is used 0 0 0 0 off off off off v1 to v5 if combinations other than the above are used, normal operation is not guaranteed. fedl9445-02 ML9445 35/84 1, the 1 st voltage multiplier circuit, 2 nd voltage multipliers circuit, v1 voltage adjustment circuit, and v/f circuit are used(all int ernal power supplies) use this combination when not using the power supply from the external. all voltages required for driving lcd are generated from the vin voltage. all internal power supplies are used. see figure 13-1. 2, only the 1 st voltage multiplier circuit, v1 voltage adju stment circuit, and v/f circuit are used (2 nd voltage multiplier circuit is not used) use this combination when not using the power supply from the external. all voltages required for driving lcd are generated from the vin voltage. the number of capacitors for voltage multiplication can be reduced by stopping the 2 nd voltage multiplier circuit. short v out1 , v h , and v out2 to use this combination. see figure 13-2. 3, only the 2 nd voltage multiplier circuit, v1 voltage adju stment circuit, and v/f circuit are used (1 st voltage multiplier circuit is not used) use this combination when the v out1 voltage can be supplied from the external. although the capacitor for the 1 st voltage multiplication is not connected, set the command to use the 1 st voltage multiplier circuit (db2 = ?0?). see figure 13-3. 4, only the v1 voltage adjustment circuit and v/f circuit are used use this combination when the v out2 voltage can be supplied from the external. the v2, v3, v4, and v5 voltages are generated, which are the lcd drive voltages generated by the internal v1 voltage adjustment circuit and v/f circuit. connect capacitors for retaining voltages to the v1 to v5 pins. the v1 voltage can be adjusted by the v1 voltage adjustment command and the electronic potentiometer command. see figure 13-4. 5, only the v/f circuit is used use this combination when the v1 volta ge can be supplied from the external. connect capacitors for retaining voltages to the v2, v3, v4, and v5 pins which output the lcd drive voltages generated by the v/f circuit. see figure 13-5. 6, only the external power supply is us ed (all internal power supplies are off) use this combination when the v1, v2, v3, v4, and v5 voltages can be supplied from the external. see figure 13-6. fedl9445-02 ML9445 36/84 ? 1 st voltage multiplier circuits the 1 st voltage multiplier circuit can multiply the vin to vss voltage by 2, 3, 4, or 5 times. fig. 7-1 to 7-4 show the circuit connections and the voltage relationships. fig. 7-1 2-time voltage multiplier circuit and voltage relationships in 2-time multiplication v in v ss v out1 vc6+ vc4+ vs2? vc5+ vc3+ vs1? 2-time voltage open open + + vc2+ open open v out = 2 v in = 10v *1 v in = 5v v s = 0 v c1 c1 multiplier circuit voltage relationship in 2-time multiplication connect capacitors between vc6+ and vs2- and between v out1 and v ss , open the vc4+, vc2+, vc3+, and vs1- pins, and short the v in and vc5+ pins to use this connection. should be used in the range of vin = 3 to 5.5 v. fig. 7-2 3-time voltage multiplier circuit and voltage relationships in 3-time multiplication v in v ss v out1 vc6+ vc4+ vs2? vc5+ vc3+ vs1? vc2+ v out = 3 v in = 15v *1 v in = 5v v s = 0 v open + + + open c1 c1 c1 3-time voltage multiplier circuit voltage relationship in 3-time multiplication connect capacitors between vc6+ and vs2-, between vc5+ and vs1-, and between v out1 and v ss , open the vc2+, and vc3+ pins, and short the v in and vc4+ pins to use this connection. should be used in the range of vin = 2.7 to 5.5 v. fedl9445-02 ML9445 37/84 fig. 7-3 4-time voltage multiplier circuit and voltage relationships in 4-time multiplication v in v ss v out1 vc6+ vc4+ vs2? vc5+ vc3+ vs1? vc2+ v out = 4 v in = 18v *1 v in = 4.5v v s = 0 v + + + + open c1 c1 c1 c1 4-time voltage multiplier circuit voltage relationship in 4-time multiplication connect capacitors between vc6+ and vs2-, between vc4+ and vs2-, between vc5+ and vs1-, and between v out1 and v ss , open the vc2+ pin, and short the v in and vc3+ pins. should be used in the range of vin = 2.7 to 4.625 v. fig. 7-4 5-time voltage multiplier circuit and voltage relationships in 5-time multiplication v in v ss v out1 vc6+ vc4+ vs2? vc5+ vc3+ vs1? vc2+ v out = 5 v in = 18.5v *1 v in = 3.7v v s = 0 v + + + + + c1 c1 c1 c1 c1 5-time voltage multiplier circuit voltage relationship in 5-time multiplication connect capacitors between vc6+ and vs2-, between vc4+ and vs2-, between vc5+ and vs1-, between vc3+ and vs1-, and between v out1 and v ss , and short the v in and vc2+ pins to use this connection. should be used in the range of vin = 2.7 to 3.7 v . *1: the voltage range of v in should be set from 6v to 18.5v so that the voltage at the pin v out does not exceed the voltage multiplier output voltage operating range. fedl9445-02 ML9445 38/84 ? 2 nd voltage multiplier circuits it consists of a voltage adjustment circuit and 2-time voltage multiplier circuit. the voltage adjustment circuit operates in v out1 voltage systems, generates v h which is the base voltage of the 2 nd voltage multiplier circuit, and generates v out2 with 2-time voltage multiplication of v h . the connection example for 2 nd voltage multiplier circuits is shown in fig. 9. fig. 9 connection examples for 2 nd voltage multiplier circuits connect capacitors between v out2 and v ss , between v h and v ss , and between vc7+ and vs3-. when you stop the 2 nd voltage multiplier circuit and operate the v1 voltage adjustment circuit with the 1 st boost output, short the v out2 pin to use v h and v out2 . v ss v out 2 + + v h vc7+ vs3- + fedl9445-02 ML9445 39/84 ? voltage adjustment circuit the voltage multiplier output v out produces the lcd drive voltage v1 via the voltage adjustment circuit. since the ML9445 incorporates a high accuracy constant voltage generator, a 128-level electronic potentiometer function, and also resistors for voltage v1 adjustment, it is possible to build a high accuracy voltage adjustment circuit with very few components. (a) when the internal resistors for voltage v1 adjustment are used it is possible to control the lcd power supply voltage v1 and adjust the intensity of lcd display using commands and without needing any external resistors, if the inte rnal voltage v1 adjustment resistors and the electronic potentiometer function are used. the voltage v1 can be obtained by the following equation a-1 or a-2 in the range of v1 fedl9445-02 ML9445 43/84 when the electronic potentiometer register value is set to db7= 1 vev=(1-( /300))? vreg =0 vev = 1 ? 0/300 ? 3.0v = 3.0v =63 vev = 1 ? 63/300 ? 3.0v = 2.360v =127 vev = 1 ? 127/300 ? 3.0v = 1.730v when vreg = 3.0 v the increment size is : 3.0 v ? 1.730 v = = 10 mv (nominal) 127 * when using the voltage v1 adjustment internal resistor s or the electronic potentiometer function, it is necessary to set at least the voltage adjustment circuit and the voltage follower circuits both in the operating state using the power control setting command. also, when the voltage multiplier circuit is off, it is necessary to supply a voltage externally to the v out pin. * the pin vr is effective only when the voltage v1 adjustment internal resistors are not used (pin irs = ?l?). leave this pin open when the voltage v1 adjustment internal resistors are being used (pin irs = ?h?). * since the input impedance of the pin vr is high, it is necessary to take noise countermeasures such as using short wiring length or a shielded wire . * the supply current increases in proportion to the pane l capacitance. when power consumption increases, the v out level may fall. the voltage (v out ? v1) should be more than 3 v. ? lcd drive voltage generator circuits the voltage v1 is converted by resistive divider to produce v2, v3, v4, and v5 voltages. v2, v3, v4, and v5 voltages are impedance ? converted by the voltage follower, and is supplied to the lcd voltage generator circuits. a bias ratio is chosen by the bias set command. table 15 relationship between lcd bias set command and v2,v3,v4,v5 lcd bias set command register value (db2, db1, db0) voltage (0, 0, 0) 1/4 bias (0, 0, 1) 1/5 bias (0, 1, 0) 1/6 bias (0, 1, 1) 1/7 bias (1, 0, 0) 1/8 bias (1, 0, 1) 1/9 bias v2 3/4 ? v1 4/5 ? v1 5/6 ? v1 6/7 ? v1 7/8 ? v1 8/9 ? v1 v3 2/4 ? v1 3/5 ? v1 4/6 ? v1 5/7 ? v1 6/8 ? v1 7/9 ? v1 v4 2/4 ? v1 2/5 ? v1 2/6 ? v1 2/7 ? v1 2/8 ? v1 2/9 ? v1 v5 1/4 ? v1 1/5 ? v1 1/6 ? v1 1/7 ? v1 1/8 ? v1 1/9 ? v1 fedl9445-02 ML9445 44/84 ? application circuits fig. 13-1 to 13-6 show reference examples of power supply circuits. (two v1 pins are described in the following examples for explanation, but they are the same.) fig. 13-1 when all internal power supplies are used vin = vdd, 5-time voltage multiplication. vin = vdd, 5-time voltage multiplication. the internal v1 voltage adjustment resistor is used. the internal v1 voltage adjustment resistor is not used. fig. 13-2 when using the 1 st voltage multiplier circuit, voltage adjustment circuit, and v/f circuit (2 nd voltage multiplier circuit is stopped) vin = vdd, 5-time voltage multiplication. the internal v1 voltage adjustment resistor is not used. vc7+ vs7- v in vc6+ vc4+ vc2+ vs2- vc5+ vc3+ vs1- vr v ss v out2 v h v out1 v1 v2 v3 v4 v5 irs + c3 c3 c3 c3 c2 c2 c2 c2 + + + + + m/ s v ss v dd c1 c1 c1 c1 c1 + + + + + + + open vc7+ vs7- v in vc6+ vc4+ vc2+ vs2- vc5+ vc3+ vs1- v1 vr v ss v out2 v h v out1 v1 v2 v3 v4 v5 irs + c3 c3 c3 c3 c2 c2 c2 c2 + + + + + m/ s v ss v dd c1 c1 c1 c1 c1 r1 r2 r3 + + + + + + + vc7+ vs7- v in vc6+ vc4+ vc2+ vs2- vc5+ vc3+ vs1- v1 vr v ss v out2 v h v out1 v1 v2 v3 v4 v5 irs c3 c3 c2 c2 c2 c2 + + + + m/ s v ss v dd c1 c1 c1 c1 r1 r2 r3 + + + + + + open open fedl9445-02 ML9445 45/84 fig. 13-3 when using the 2 nd voltage multiplier circuit, voltage adjustment circuit, and v/f circuit (1 st voltage multiplier circuit is stopped) the voltage multiplier circuits are not used. the internal v1 voltage adjustment resistor is used. fig. 13-4 when using only the voltage adjustment circuit and v/f circuit (the 1 st and 2 nd voltage multiplier circuits are stopped) the voltage multiplier circuits are not used. the internal v1 voltage adjustment resistor is used. vc7+ vs7- v in vc6+ vc4+ vc2+ vs2- vc5+ vc3+ vs1- vr v ss v out2 v h v out1 v1 v2 v3 v4 v5 irs + c3 c3 c3 c2 c2 c2 c2 + m/ s v ss v dd c1 + + + + + + open v out1 open open open open open open open vc7+ vs7- v in vc6+ vc4+ vc2+ vs2- vc5+ vc3+ vs1- vr v ss v out2 v h v out1 v1 v2 v3 v4 v5 irs c1 c2 c2 c2 c2 m/ s v ss v dd + + + + + open open open open open open open open open open external open open power supply fedl9445-02 ML9445 46/84 fig. 13-5 when using only v/f circuit (the 1 st and 2 nd voltage multiplier circuits and the voltage adjustment circuit are stopped) the voltage multiplier circuits are not used. the internal v1 voltage adjustment resistor is used . fig. 13-6 when not using the internal power supply (all supplied from the external) the voltage multiplier circuits are not used. the internal v1 voltage adjustment resistor is used. vc7+ vs7- v in vc6+ vc4+ vc2+ vs2- vc5+ vc3+ vs1- vr v ss v out2 v h v out1 v1 v2 v3 v4 v5 irs c2 c2 c2 c2 m/ s v ss v dd + + + + open open open open open open open open open open open open open external power supply vc7+ vs7- v in vc6+ vc4+ vc2+ vs2- vc5+ vc3+ vs1- vr v ss v out2 v h v out1 v1 v2 v3 v4 v5 irs m/ s v ss v dd open open open open open open open open open open open open open external power supply fedl9445-02 ML9445 47/84 ? capacitor setting reference values the optimal values for the capacitors c1 and c2 shown in the reference examples of power supply circuits vary depending on the size of the liquid crystal panel. determine the capacitance by displaying a pattern with a heavy load and selecting a value that stabilizes the lcd drive voltage. table 16 shows the setting reference values for capacitors. table 16 capacitor setting reference values symbol descriptions reference setting value [ f] c1 capacity for supply voltage regulation 1.0 4.7 c2 liguid crystal drive voltage retaining(smoothing) capacitor 0.47 4.7 c3 capacity for set-up circuits 1.0 4.7 if the lcd panel is so large that the satisfactory display quality cannot be obtained by changing the capacitor values, stop the internal power supply circuit, and supply the lcd drive voltage from the external. ? notes on cog mounting when mounting the cog, there are resistance components caused by ito wiring between the ic or external connecting parts (capacitor, resistor) and the power supply. these resistance components may degrade the liquid crystal display quality or may malfunction the ic. when designing a liquid crystal module, take the following three points into account and evaluate them under the practical prerequisites. 1, trace resistance of voltage multiplying system pins this ic's voltage multiplier circuits are switched with a transistor with very low on resistance. in mounting the cog, ito's trace resistance gets into the switching transi stor in series and controls the voltage multiplication ability. pay attention to the proper wiring to each capacitor, including making the ito wiring as thick as possible. 2, trace resistance of power supply pins when current flow occurs momentarily as in case of the display switching, the supply voltage may drop momentarily in synchronization with the occurrence of current flow. if the ito's wiring resistance to the power supply pin is high at this time, the supply voltage fluctuates greatly inside the ic and may malfunction the ic. try to reduce the wiring impedance of the power supply line as much as possible to supply stabilized power to the ic. 3, creation of module sample with changed sheet resistance evaluate the sample with the ito trace resistance value changed, and select a sheet resistance material which has as much operating margin as possible. 4, recommended ito resistance value vdd,vss,vin b> 50 fedl9445-02 ML9445 49/84 application circuits master operation: m/s="h" parallel data input: p/s="h" 80-series mpu interface: c86="l" internal oscillation circuit: cls="h" v1 adjusting - internal resistor is used : irs="h" 1 st voltage multiplier circuit is used (see figure 7-2) 2 nd voltage multiplier circuit is used c0=0.1uf, c1=1.0uf, c2=1.0uf, c3=4.7uf ML9445 180x65 dot test1 vss_o sdaack sync fr cl dof cs1 cs2 res a0 vss_o wr rd vdd_o db0 db1 db2 db3 db4 db5 db6 db7 vch svd2 test2 vdd_o m/ s cls c86 p/ s irs test3 vss vdd vin vc3+ vc5+ vs1- vc2+ vc4+ vs2- vc6+ vout1 vh vs3- vc7+ vout2 vr vrs v1 v2 v3 v4 v5 cs1 res a0 wr rd db0 db1 db2 db3 db4 db5 db6 db7 svd2 vss vdd open open open open open open open open open + c3 + c3 + c1 + c1 + c1 + c3 connector open + c3 + c2 + c2 + c2 + c2 c1 c0 fedl9445-02 ML9445 50/84 ? cascade connection example it is possible to expand the display area by us ing the ML9445 in a multiple chip configuration. * when the internal oscillator circuit is used. * it is recommended to supply the lcd drive power supply from the external. * it is possible to use the master-side internal power supply to supply the power to the slave. however, in this case, the required voltage may not be obtained due to the ito trace resistance or the lcd panel load. make a thorough evaluation before using this configuration. ? initial setting note: if electric charge remains in smoothing capacitor co nnected between the lcd driver voltage output pins (v1 to v5) and the v ss pin, a malfunction might occur: the display screen gets dark for an instant when powered on. to avoid a malfunction at power-on, it is recomme nded to follow the flowchart in the ?examples of settings for the instructions? section in page 63. ML9445 master fr sync cl dof ML9445 slave m/s m/s v dd v ss seg seg com com lcdpanel 36065 dots fedl9445-02 ML9445 51/84 list of operation dbn no operation 7 6 5 4 3 2 1 0 a0 rd wr comment display off 1 0 1 0 1 1 1 0 0 1 0 1 display on 1 0 1 0 1 1 1 1 0 1 0 lcd display: off when db0 = 0 on when db0 = 1 forward 1 0 1 0 0 1 1 0 0 1 0 2 display reverse 1 0 1 0 0 1 1 1 0 1 0 forward or reverse lcd display mode forward when db0 = 0 reverse when db0 = 1 off (normal display) 1 0 1 0 0 1 0 0 0 1 0 3 lcd all-on display on 1 0 1 0 0 1 0 1 0 1 0 lcd normal display when db0 = 0 all-on display when db0 = 1 1 1 0 0 0 1 0 0 0 1 0 4 common output state select 1 1 0 0 0 1 0 1 0 1 0 selects the common output scanning direction. forward when db = 0 reverse when db0 = 1 1 0 0 0 1 0 1 0 0 1 0 5 display start line set (2-byte command) * * address 0 1 0 the display starting line address in the display ram is set. 6 page address set (2-byte command) 1 0 1 1 0 0 0 0 * * * address 0 1 0 the page address in the display ram is set. column address set (upper bits) 0 0 0 1 address (upper bits) 0 1 0 the upper 4 bits of the column address in the display ram is set. 7 column address set (lower bits) 0 0 0 0 address (lower bits) 0 1 0 the lower 4 bits of the column address in the display ram is set. 8 display data write write data 1 1 0 writes data to the display data ram. 9 display data read read data 1 0 1 reads data from the display data ram. 1 0 0 0 0 1 0 0 0 1 0 10 display data input direction select 1 0 0 0 0 1 0 1 0 1 0 display ram data input direction. column direction when db0=1 page direction when db0=1 forward 1 0 1 0 0 0 0 0 0 1 0 11 adc select reverse 1 0 1 0 0 0 0 1 0 1 0 correspondence to the segment output for the display data ram address. forward when db0 = 0 reverse when db0 = 1 12 n-line inversion drive register set (2-byte command) 0 0 1 1 0 0 0 0 * * * invert line count 0 1 0 line invert drive. set the line count. off 1 1 1 0 0 1 0 0 0 1 0 13 n-line inversion drive on 1 1 1 0 0 1 0 1 0 1 0 resets the line invert drive. n-line off when db0 = 0 n-line on when db1 = 1 0 1 1 0 1 1 0 1 0 1 0 * * number of duty 0 1 0 14 display duty set (3-byte command) * * start line 0 1 0 display duty set. 15 read-modify-write 1 1 1 0 0 0 0 0 0 1 0 incrementing column address during a write: +1 during a read: 0 16 end 1 1 1 0 1 1 1 0 0 1 0 releases the read-modify-write state. off 1 0 1 0 1 0 1 0 0 1 0 17 built-in osc on 1 0 1 0 1 0 1 1 0 1 0 built-in oscillator circuit operation. off when db0 = 0 on when db1 = 1 18 built-in oscillator frequency select 0 1 1 1 frequency 0 1 0 built-in oscillator frequency select. 0 0 1 0 1 0 0 0 0 1 0 19 power control set (2-byte command) * * * * state 0 1 0 select built-in power supply operation state. fedl9445-02 ML9445 52/84 20 voltage v1 adjustment internal resistance ratio set 0 0 1 0 0 resistance ratio setting 0 1 0 selects the internal resistor ratio. dbn no operation 7 6 5 4 3 2 1 0 a0 rd wr comment 0 1 0 1 0 0 0 0 0 1 0 21 lcd bias set (2-byte command) * * * * * bias 0 1 0 sets the lcd drive voltage bias ratio. 1 0 0 0 0 0 0 1 0 1 0 22 electronic volume set (2-byte command) electronic volume 0 1 0 sets data in the electronic potentiometer register to adjust the v1 output voltage. off 1 1 1 0 1 0 1 0 0 1 0 23 discharge on 1 1 1 0 1 0 1 1 0 1 0 discharges power supply circuit connection capacitor. off when db0 = 0 on when db1 = 1 off 1 0 1 0 1 0 0 0 0 1 0 24 power save on 1 0 1 0 1 0 0 1 0 1 0 power save off when db0 = 0 on when db1 = 1 25 temperature gradient select 0 1 0 0 1 gradient 0 1 0 setting of temperature gradient of lcd voltage. 26 status read * * * * * gradient 0 0 1 issues the temperature gradient select bit. 27 reset 1 1 1 0 0 0 1 0 0 1 0 reset command off 0 1 1 0 1 0 0 0 0 1 0 28 temperature sensor on 0 1 1 0 1 0 0 1 0 1 0 temperature sensor off when db0 = 0 on when db0 = 1 1 1 0 0 0 0 0 0 0 1 0 29 common output direction select 1 1 0 0 0 0 0 1 0 1 0 db=0 : com0 com1 com63 db=1 : com0 com32 com33 com31 com63 0 1 0 1 0 1 0 1 0 1 0 30 multiplier clock frequency select (2-byte command) * * * * * * frequency 0 1 0 multiplier clock frequency select 31 nop 1 1 1 0 0 0 1 1 0 1 0 non-operation command *: invalid data (input: don?t care, output: unknown) fedl9445-02 ML9445 53/84 descriptions of operation display on/off (write) this is the command for controlling the turning on or off the lcd panel. the lcd display is turned on when a ?1? is written in bit db0 and is turned off when a ?0? is written in this bit. a0 db7 db6 db5 db4 db3 db2 db1 db0 display on 0 1 0 1 0 1 1 1 1 display off 0 1 0 1 0 1 1 1 0 forward/reverse display mode (write) it is possible to toggle the display on and off condition without changing the contents of the display data ram. in this case, the contents of the display data ram will be retained. a0 db7 db6 db5 db4 db3 db2 db1 db0 ram data forward 0 1 0 1 0 0 1 1 0 display on when ?h? reverse 0 1 0 1 0 0 1 1 1 display on when ?l? lcd display all-on on/off (write) using this command, it is possible to forcibly turn on all displays irrespective of the contents of the display data ram. in this case, the contents of the display data ram will be retained. also, all displays can be in white in combination with a display inversion command. a0 db7 db6 db5 db4 db3 db2 db1 db0 all-on display off (normal display) 0 1 0 1 0 0 1 0 0 all-on display on 0 1 0 1 0 0 1 0 1 the power save mode will be entered into when the display all-on on command is executed in the display off condition. common output state select (write) this command is used for selecting the scanning direction of the common output pins. scanning direction a0 db7 db6 db5 db4 db3 db2 db1 db0 forward com0 com63 0 1 1 0 0 0 1 0 0 reverse com63 com0 0 1 1 0 0 0 1 0 1 *: invalid data fedl9445-02 ML9445 54/84 display start line set (2-byte command) this command specifies the display starting line address in the display data ram. normally, the topmost line in the display is specified using the display start line set command. it is possible to scroll the display screen by dynamically changing the address using the display start line set command. this command is a 2-byte command to be used together with the display start line set mode set command and display start line set register set command. so, be sure to set the both commands continuously. ? display start line set mode set (write) when this command is input, the display start line set command becomes valid. once the display start line set mode is selected, any command other than the display start line set command cannot be used. this status is released when any data is stored in the register by the display start line set command. a0 db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 0 0 1 0 1 0 ? display start line set register set (write) setting of data to low order 7 bits of the display start line register by this command allows specification of the display start line address of the display data ram. in addition, the most significant bit is for data setting of com output pins only for indicators (coms), and the data of 80h for 0 and 81h for 1 is for indicators. after the display start line register is set by inputting this command, the display start line mode is released. line address coms data a0 db7 db6 db5 db4 db3 db2 db1 db0 00h 0 0 0 0 0 0 0 0 0 01h 0 0 0 0 0 0 0 0 1 02h 0 0 0 0 0 0 0 1 0 03h 0 0 0 0 0 0 0 1 1 7eh 0 0 1 1 1 1 1 1 0 7fh 80h 0 0 1 1 1 1 1 1 1 00h 0 1 0 0 0 0 0 0 0 01h 0 1 0 0 0 0 0 0 1 02h 0 1 0 0 0 0 0 1 0 03h 0 1 0 0 0 0 0 1 1 7eh 0 1 1 1 1 1 1 1 0 7fh 81h 0 1 1 1 1 1 1 1 1 sequence of setting the display start line set display start line mode the display start line set mode is released set display start line register fedl9445-02 ML9445 55/84 page address set (2-byte command) this command specifies the page address which corresponds to the lower address when accessing the display data ram from the mpu side. it is possible to access any required bit in the display data ram by specifying the page address and the column address. this command is a 2-byte command to be used together with the page address mode set command and page address resister set command. so, be sure to set the both commands continuously. ? page address mode set (write) when this command is input, the page address mode set command becomes valid. once the page address mode is selected, any command other than the page address resister set command cannot be used. this status is released when any data is stored in the register by the page address resister set command. a0 db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 1 1 0 0 0 0 ? page address register set (write) when a 5-bit data is set in the page address register by this command, the line address takes the following value. after the page address register is set by inputting this command, the display page address set mode is released. page address a0 db7 db6 db5 db4 db3 db2 db1 db0 page 0 0 * * * 0 0 0 0 0 page 1 0 * * * 0 0 0 0 1 page 3 0 * * * 0 0 0 1 0 page 16 0 * * * 1 0 0 0 0 page 17 0 * * * 1 0 0 0 1 *: invalid data note: do not specify values that do not exist as an address. sequence of setting the page address register set page address mode the display start line set mode is released set page address register fedl9445-02 ML9445 56/84 column address set (write) this command specifies the column address of the disp lay data ram. the column address is specified by successively writing the upper 4 bits and the lower 4 bits. a0 db7 db6 db5 db4 db3 db2 db1 db0 upper bits 0 0 0 0 1 a7 a6 a5 a4 lower bits 0 0 0 0 0 a3 a2 a1 a0 column address a7 a6 a5 a4 a3 a2 a1 a0 00h 0 0 0 0 0 0 0 0 01h 0 0 0 0 0 0 0 1 02h 0 0 0 0 0 0 1 0 b2h 1 0 1 1 0 0 1 0 b3h 1 0 1 1 0 0 1 1 note: do not specify values that do not exist as an address. display data write (write) this command writes an 8-bit data at the specified address of the display data ram. after writing, column address or page address is automatically incremented +1 by the display data input direction select command. this enables the mpu to write the display data continuously. a0 db7 db6 db5 db4 db3 db2 db1 db0 1 write data display data read (read) this command read the 8-bit data from the specified addre ss of the display data ram. since the column address is automatically incremented (by +1) after reading the data, the mpu can read successive display data from the display data ram. further, one dummy read operation is necessary immediately after setting the column data or page data. the display data cannot be read out when the serial interface is being used. a0 db7 db6 db5 db4 db3 db2 db1 db0 1 read data display data input direction select (write) this command sets the direction where the display ram address number is automatically incremented. a0 db7 db6 db5 db4 db3 db2 db1 db0 column 0 1 0 0 0 0 1 0 0 page 0 1 0 0 0 0 1 0 1 fedl9445-02 ML9445 57/84 adc select (segment driver direction select) (write) using this command it is possible to reverse the relationship of correspondence between the column address of the display data ram and the segment driver output. it is possible to reverse the sequence of the segment driver output pin by the command. a0 db7 db6 db5 db4 db3 db2 db1 db0 forward 0 1 0 1 0 0 0 0 0 reverse 0 1 0 1 0 0 0 0 1 n-line inversion drive regi ster set (2-byte command) this command sets the number of inversion lines of the liquid crystal ac drive to the register and starts line inversion drive. this command is a 2-byte command to be used together with the n-line inversion drive register mode set command and the n-line inversion drive register set command. so, be sure to set the both commands continuously. ? n-line inversion drive register mode set (write) when this command is input, the n-line inversion drive register set command becomes valid. once the n-line inversion drive register mode is sel ected, any command other than the n-line inversion drive register set command cannot be used. this status is released when any data is stored in the register by the n-line inversion drive register set command. a0 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 1 0 0 0 0 ? n-line inversion drive register set (write) setting of 5-bit data in the n-line inversion drive register by this command allows specification of the number of inversion lines. the n-line inversion drive register mode is re leased after the n-line inversion drive register is set by inputting this command. number of line reversal a0 db7 db6 db5 db4 db3 db2 db1 db0 1 * * * * 0 0 0 0 0 2 * * * * 0 0 0 0 1 3 * * * * 0 0 0 1 0 31 * * * * 1 1 1 1 0 32 * * * * 1 1 1 1 1 *: invalid data fedl9445-02 ML9445 58/84 sequence of setting the display start line n-line inversion drive on/off (write) this command provides on/off control of n-line inverting drive. a0 db7 db6 db5 db4 db3 db2 db1 db0 off 0 1 1 1 0 0 1 0 0 on 0 1 1 1 0 0 1 0 1 display duty set (3-byte command) this command allows change display duty. setting of the start line and duty of common output allows display of arbitrary location and the number of lines. com output only for indicators (coms) is output always after end line output. in addition, if the built-in oscillator circuit is used, execute master clock division depending on the setting. 1/65 to 1/50 duty: no division, 1/49 to 1/34 duty: 2/3 division, 1/33 to 1/18: 1/2 division, 1/18 duty or less: 1/4 division this command is a 3-byte command to be used in combination with the display duty mode set command, display duty register set command, start line register set command; and therefore be sure to use the three commands continuously. ? display duty mode set (write) when this command is input, the display duty register set command and start line register set command become valid. once the display duty mode is selected, any command other than the display duty register set command/start line register set command cannot be used. this status is re leased when any data is stored in the register by the display duty register set command and start line register set command. a0 db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 1 1 0 1 n-line inversion drive mode n-line inversion drive set mode is released n-line inversion drive register fedl9445-02 ML9445 59/84 ? display duty register set (write) when a 6-bit data is set in the display duty register by this command, the display duty address takes the following value. display duty a0 db7 db6 db5 db4 db3 db2 db1 db0 1/3 0 * * 0 0 0 0 0 * 1/4 0 * * 0 0 0 0 1 0 1/5 0 * * 0 0 0 0 1 1 1/64 0 * * 1 1 1 1 1 0 1/65 0 * * 1 1 1 1 1 1 *: invalid data ? start line register set (write) when a 6-bit data is set in the start line register by th is command, the start line address takes the following value. when the status of common output is reversed, the commons in parentheses first will start. after the start line register is set by inputting this command, the display duty set mode is released. start line a0 db7 db6 db5 db4 db3 db2 db1 db0 com0 (com63) 0 * * 0 0 0 0 0 0 com1 (com62) 0 * * 0 0 0 0 0 1 com2 (com61) 0 * * 0 0 0 0 1 0 com3 (com60) 0 * * 0 0 0 0 1 1 com62 (com1) 0 * * 1 1 1 1 1 0 com63 (com0) 0 * * 1 1 1 1 1 1 *: invalid data sequence of setting the display duty set register set display duty mode the display start line set mode is released set start line register set display duty register fedl9445-02 ML9445 60/84 read modify write (write) this command is used in combination with the end command. when this command is issued once, the page address and column address are not changed when the displa y data read command is issued, but is incremented (by +1) only when the display data write command is issued. (the incremental direction can be set by the display data input direction select command.) this condition is maintained until the end command is issued. when the end command is issued, the column address is restored to the address that was effective at the time the read modify write command was issued last. using this function, it is possible to reduce the overhead on the mpu when repeatedly changing the data in special display area such as a blinking cursor. a0 db7 db6 db5 db4 db3 db2 db1 db0 0 1 1 1 0 0 0 0 0 end (write) this command releases the read-modify-write mode and restores the page address and column address to the value at the beginning of the mode. a0 db7 db6 db5 db4 db3 db2 db1 db0 0 1 1 1 0 1 1 1 0 read-modify-write mode set n n+1 n+2 n + 3 .... n+m n column address end restored page address or built-in oscillator circuit on/off (write) this command starts the built-in oscillator circuit operation. it is enabled only in the master operation mode (m/ s =high) when built-in oscillator circuit is valid (cls=high). a0 db7 db6 db5 db4 db3 db2 db1 db0 off 0 1 0 1 0 1 0 1 0 on 0 1 0 1 0 1 0 1 1 fedl9445-02 ML9445 61/84 operation clock frequency select (write) this command sets the dividing rate of the internal operation clock for the built-in oscillator frequency fosc. it is enabled only when the built-in oscillator circuit in on. it is divided together with the display duty set division. when the built-in oscillator circuit is off, the external clock f ext to be input to cl pin directly becomes the internal operation clock. ratio of dividing frequency a0 db7 db6 db5 db4 db3 db2 db1 db0 1/4 0 0 1 1 1 0 0 0 0 1/4.5 0 0 1 1 1 0 0 0 1 1/5 0 0 1 1 1 0 0 1 0 1/5.5 0 0 1 1 1 0 0 1 1 1/6 0 0 1 1 1 0 1 0 0 1/7 0 0 1 1 1 0 1 0 1 1/8 0 0 1 1 1 0 1 1 0 1/10 0 0 1 1 1 0 1 1 1 1/12 0 0 1 1 1 1 0 0 0 1/14 0 0 1 1 1 1 0 0 1 1/16 0 0 1 1 1 1 0 1 0 1/18 0 0 1 1 1 1 0 1 1 1/20 0 0 1 1 1 1 1 0 0 1/24 0 0 1 1 1 1 1 0 1 1/28 0 0 1 1 1 1 1 1 0 1/32 0 0 1 1 1 1 1 1 1 frame frequencies for typical numbers of display lines are listed below. frame frequency [hz] db3 db2 db1 db0 65 line 50 line 49 line 34 line 33 line 18 line 17 line 0 0 0 0 200 260 177 255 197 361 191 0 0 0 1 178 231 157 227 175 321 170 0 0 1 0 160 208 141 204 158 289 153 0 0 1 1 145 189 129 185 143 263 139 0 1 0 0 133 173 118 170 131 241 127 0 1 0 1 114 149 101 146 113 206 109 0 1 1 0 100 130 88 127 98 181 96 0 1 1 1 80 104 71 102 79 144 76 1 0 0 0 67 87 59 85 66 120 64 1 0 0 1 57 74 51 73 56 103 55 1 0 1 0 50 65 44 64 49 90 48 1 0 1 1 44 58 39 57 44 80 42 1 1 0 0 40 52 35 51 39 72 38 1 1 0 1 33 43 29 42 33 60 32 1 1 1 0 29 37 25 36 28 52 27 1 1 1 1 25 33 22 32 25 45 24 the table above shows the values at 25c fedl9445-02 ML9445 62/84 the calculation formula for frame frequencies is shown below. it depends on the number of duty sets. duty lcd frame frequency (f fr ) 1/65 to 1/50 duty f osc /(16*n*l) 1/49 to 1/34 duty f osc *(2/3) /(16*n*l) 1/33 to 1/18 duty f osc *(1/2) /(16*n*l) 1/17 or less f osc *(1/4) /(16*n*l) ratio of dividing frequency: n , number of display line : l power control set (2-byte command) this command set the functions of the power supply circuits. this command is a 2-byte command to be used together with the power control mode set command and power control register set command. ? power control mode set (write) when this command is issued, the power control register set command becomes effective. once the power control mode is set, it is not possible to issue any command other than the power control register set command. this condition is released after data has been set in the register using the power control register set command. a0 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 1 0 0 0 ? power control register set (write) when a power supply circuit is set in the power control register by this command, the line address takes the following value. after the display start line is set by inputting this command, the power control set mode is released. a0 db7 db6 db5 db4 db3 db2 db1 db0 2 nd voltage multiplier circuit: off 2 nd voltage multiplier circuit: on 0 1 1 st voltage multiplier circuit: off 1 st voltage multiplier circuit: on 0 1 voltage adjustment circuit: off voltage adjustment circuit: on 0 1 voltage follower circuits: off voltage follower circuits: on 0 * * * * 0 1 *: invalid data sequence of setting the power control register set power control mode the power control mode is released set power control register fedl9445-02 ML9445 63/84 voltage v1 adjustment internal resistor ratio set this command sets the ratios of the internal resistors for adjusting the voltage v1. resistor ratio a0 db7 db6 db5 db4 db3 db2 db1 db0 2.5 0 0 0 1 0 0 0 0 0 3.0 0 0 0 1 0 0 0 0 1 3.5 0 0 0 1 0 0 0 1 0 4.0 0 0 0 1 0 0 0 1 1 4.5 0 0 0 1 0 0 1 0 0 5.0 0 0 0 1 0 0 1 0 1 5.5 0 0 0 1 0 0 1 1 0 6.0 0 0 0 1 0 0 1 1 1 note: because this lsi has temperature gradient, v1 rises at lower temperatures. when using v1 gain of 6 times, adjust the built-in electronic potentiometer so that v1 does not exceed 18.5 v. lcd bias set (2-byte command) this command is used for selecting the bias ratio of the voltage necessary for driving the lcd device or panel. this command is a 2-byte command to be used together with the lcd bias set command and lcd bias register set command. ? lcd bias mode set (write) when this command is issued, the lcd bias register set command becomes effective. once the lcd bias mode is set, it is not possible to issue any command other than the lcd bias register set command. this condition is released after data has been set in the register using the power lcd bias register set command. a0 db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 0 fedl9445-02 ML9445 64/84 ? lcd bias register set (write) the bias ratio is set with setting of data to the lcd bias register with this command. after this command is input and the lcd bias register is set, the lcd bias mode is released. lcd bias a0 db7 db6 db5 db4 db3 db2 db1 db0 1/4 bias 0 * * * * * 0 0 0 1/5 bias 0 * * * * * 0 0 1 1/6 bias 0 * * * * * 0 1 0 1/7 bias 0 * * * * * 0 1 1 1/8 bias 0 * * * * * 1 0 0 1/9 bias 0 * * * * * 1 0 1 *: invalid data (1,1,0) and (1,1,1) settings are forbidden. sequence of setting the lcd bias register set lcd bias mode the lcd bias mode is released set lcd bias register fedl9445-02 ML9445 65/84 electronic potentiome ter (2-byte command) this command is used for controlling the lcd drive voltage v1 output by the voltage adjustment circuit of the internal lcd power supply and for adjusting the intensity of the lcd display. this is a two-byte command consisting of the electronic potentiometer mode set command and the electronic potentiometer register set command, both of which should always be issued successively as a pair. ? electronic potentiometer mode set (write) when this command is issued, the electronic potentiometer register set command becomes effective. once the electronic potentiometer mode is set, it is not possible to issue any command other than the electronic potentiometer register set command. this condition is released after data has been set in the register using the electronic potentiometer register set command. a0 db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 0 0 0 0 0 1 ? electronic potentiometer register set (write) by setting a 7-bit data in the electronic potentiometer register using this command, it is possible to set the lcd drive voltage v1 to one of the 128 voltage levels. the electronic potentiometer mode is released after some data has been set in the electronic potentiometer register using this command. S v a0 db7 db6 db5 db4 db3 db2 db1 db0 127 0 0 0 0 0 0 0 0 0 126 0 0 0 0 0 0 0 0 1 125 0 0 0 0 0 0 0 1 0 124 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 1 1 0 0 small 0 0 1 1 1 1 1 1 1 127 0 1 0 0 0 0 0 0 0 126 0 1 0 0 0 0 0 0 1 125 0 1 0 0 0 0 0 1 0 124 0 1 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 large 0 1 1 1 1 1 1 1 1 sequence of setting the electronic potentiometer register: electronic potentiometer mode set electronic potentiometer register set the electronic potentiometer mode is released fedl9445-02 ML9445 66/84 discharge on/off (write) this command discharges the capacitors connected to the power supply circuit. a0 db7 db6 db5 db4 db3 db2 db1 db0 off 0 1 1 1 0 1 0 1 0 on 0 1 1 1 0 1 0 1 1 this command short circuits each liquid crystal potential (v1 to v5) and vss. when voltage is supplied to each liquid crystal drive potential externally, be sure to turn off the external power before executing this command. power save on/off (write) this command establishes the power save mode, thereby ensuring a substantial reduction of current consumption. a0 db7 db6 db5 db4 db3 db2 db1 db0 off 0 1 0 1 0 1 0 0 0 on 0 1 0 1 0 1 0 0 1 in the power save status, the display data and operation status before power save activation are held, and the display data ram can be accessed from mpu. the power save off command is to release the power save status, and it returns to the status before the power save activation. if built-in power supply is used, it is turned on after the power save off command execution, and after a fixed time period for stabilization of the output voltage, the display operation is started. the internal conditions in the power save mode are as follows: (1) stop of internal oscillator circuit. (2) stop of lcd power supply circuit. (3) stop of liquid crystal drive circuit (vss level output is issued as the segment and common driver output). (4) operation of vch generation circuit and temperature sensor circuit. temperature gradient set this command sets the temperature gradient characteristics of the liquid crystal drive voltage output from the built-in power supply circuit from eight states to one state. the temperature gradient of the liquid crystal drive voltage can be set according to the liquid cr ystal temperature gradient to be used. temperature gradient [%/c] a0 db7 db6 db5 db4 db3 db2 db1 db0 0.00 0 0 1 0 0 1 0 0 0 -0.03 0 0 1 0 0 1 0 0 1 -0.06 0 0 1 0 0 1 0 1 0 -0.08 0 0 1 0 0 1 0 1 1 -0.10 0 0 1 0 0 1 1 0 0 -0.13 0 0 1 0 0 1 1 0 1 -0.15 0 0 1 0 0 1 1 1 0 -0.18 0 0 1 0 0 1 1 1 1 fedl9445-02 ML9445 67/84 status read (read) this command reads out the temperature gradient select bit set on the register. a0 db7 db6 db5 db4 db3 db2 db1 db0 0 * * * * * t1 t2 t3 *: invalid data reset (write) this command initializes the display start line number, column address, page address, common output state, voltage v1 adjustment internal resistor ratio and the electronic potentiometer function, and also releases the read-modify-write mode or the test mode. this command does not affect the contents of the display data ram. the reset operation is made after issuing the reset command. the initialization after switching on the power is carried out by the reset signal input to the res pin. a0 db7 db6 db5 db4 db3 db2 db1 db0 0 1 1 1 0 0 0 1 0 temperature sensor on/off (write) on/off of a temperature sensor is specified with this command. a0 db7 db6 db5 db4 db3 db2 db1 db0 off 0 0 1 1 0 1 0 0 0 on 0 0 1 1 0 1 0 0 1 the temperature sensor circuit is controlled independently from power save command. common output direction select (write) this command sets the direction of the common output pin. direction a0 db7 db6 db5 db4 db3 db2 db1 db0 normal type 0 1 1 0 0 0 1 0 0 comb type 0 1 1 0 0 0 1 0 1 normal type: com0 com1 ?. com63 comb type: com0 com32 com1 com33 ?. com31 com63 fedl9445-02 ML9445 68/84 multiplier clock frequency select (2-byte command) this command selects the multiplier clock frequency of the 1 st and 2 nd voltage multiplier circuits. this command is a 2-byte command to be used together with the multiplier clock frequency select mode set command and the multiplier clock frequency select register set command. so, be sure to set the both commands continuously. ? multiplier clock frequency select mode set (write) when this command is input, the multiplier clock frequency select register set command becomes valid. once the multiplier clock frequency select mode is selected, any command other than the multiplier clock frequency select register set command cannot be used. this status is released when any data is stored in the register by the multiplier clock frequency select register set command. a0 db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 0 1 ? multiplier clock frequency register set (write) setting of data in the multiplier clock frequency select register by this command allows specification of the multiplier clock frequency. the multiplier clock frequency select mode is released when the multiplier clock frequency select register is set by inputting this command. frequency internal clock external clock a0 db7 db6 db5 db4 db3 db2 db1 db0 fosc/64 fext/8 0 0 0 0 0 0 0 0 0 fosc/32 fext/4 0 0 0 0 0 0 0 0 1 fosc/16 fext/2 0 0 0 0 0 0 0 1 * sequence of setting the multiplier clock frequency register: nop (write) this is a no operation command. a0 db7 db6 db5 db4 db3 db2 db1 db0 0 1 1 1 0 0 0 1 1 multiplier clock frequency mode set multiplier clock frequency register set the multiplier clock frequency mode is released fedl9445-02 ML9445 69/84 initialized condition using the res pin this lsi goes into the initialized condition when the res input goes to the ?l? level. the initialized condition consists of the following conditions. (1) display off (2) forward display mode (3) all-on display off (4) common output state: forward (5) display start line: set to 1 st line, indicator address: set to 80h (6) page address: set to 0 page (7) column address: set to 0 address (8) display data input direction: column direction (9) adc select: incremented (adc command db0 = ?l?) (10) n-line inversion drive: off (11) n-line reversal number register: (db4, db3, db2, db1, db0) = (1, 0, 0, 0, 0) (12) display duty set: 1/65duty, start line com0 (13) read-modify-write: off (14) built-in oscillation circuit: off (15) oscillation frequency register: (db4, db3, db2, db1, db0) = (0, 0, 0, 0) (16) power control register: (db4, db3, db2, db1, db0) = (0, 0, 0, 0) (17) voltage v1 adjustment internal resistor ratio register: (db2, db1, db0) = (1, 0, 0) (18) lcd power supply bias ratio: 1/9 bias (19) the electronic potentiometer register set mode is released. electronic potentiometer register: (db5, db4, db3, db2, db1, db0) = (1, 0, 0, 0, 0, 0) (20) discharge: off (21) power save: off (22) temperature gradient resistor: (db2, db1, db0) = (0, 0, 0) (0.00%/c) (23) register data in the serial interface: clear (24) temperature sensor: off (25) common output direction: normal (26) multiplier clock frequency: (db1, db0)=(0,0) on the other hand, when the reset command is used, only the conditions (6) to (7), (13) above are set. as is shown in the ?mpu interface (example for reference)?, the res pin is connected to the reset pin of the mpu and the initialization of this lsi is made simultaneously with the resetting of the mpu. this lsi always has to be reset using the res pin at the time the power is switched on. also, excessive current can flow through this lsi when the control signal from the mpu is in the high impedance state. it is necessary to take measures to ensure that the input pins of this lsi do not go into the high impedance state after the power has been switched on. fedl9445-02 ML9445 70/84 examples of settings for the instructions initial setup *(a): carry out power control set within 5ms after releasing the reset state. the 5ms duration changes depending on the panel characteristics and the value of the smoothing capacitor. we recommend verification of operation using an actual unit. *(b): when trace resistance in cog mounting does not exist, wait for over 300 ms. since this value varies with trace resistance, v1, smoothing capacitors, or voltage multiplier capacitors in cog mounting, confirm operation on an actual circuit board when using this lsi. notes: sections to be referred to *1: functional description ?reset circuit? *2: description of operation ?forward/reverse display mode? *3: description of operation ?lcd display all-on on/off? *4: description of operation ?common output status select? *5: description of operation ?display start line set? *6: description of operation ?adc select? *7: description of operation ?display duty set? *8: description of operation ?n-line inversion drive register set? v dd -v ss power supply on when the pin r es = ?l? power supply stabilization release reset state ( r es pin = ?h?) initial settings state (default) *1 wait for more than 300 ms function setting using command input (user settings) display forward/reverse lcd display all-on on/off common output state select display start line set a dc select display duty set *2 *3 *4 *5 function setting using command input (user settings) n-line inversion drive register set n-line inversion drive on/off *8 *9 *(a) function setting using command input (user settings) lcd bias set voltage v1 adjustment internal resistor ratio set electronic potentiometer temperature gradient set power control set initial setting state complete *(b) *6 *7 function setting using command input (user settings) built-in oscillator frequency select built-in oscillator circuit on/off *10 *11 *12 *13 *14 *15 *16 when the external lcd power supply circuit is used external lcd power supply entry wait for stabilization of the external lcd power supply fedl9445-02 ML9445 71/84 *9: description of operation ?n-line inversion drive on/off? *10: description of operation ?built-in oscillator frequency select? *11: description of operation ?built-in oscillator circuit on/off? *12: description of operation ?lcd bias set? *13: functional description ?power supply circuit?, operation description ?voltage v1 adjustment internal resistor ratio set? *14: functional description ?power supply circuit?, operation description ?electronic potentiometer? *15: operation description ?temperature gradient set? *16: functional description ?power supply circuit?, operation description ?power control set? fedl9445-02 ML9445 72/84 data display notes: sections to be referred to *17: description of operation ?display data input direction select? *18: description of operation ?page address set? *19: description of operation ?column address set? *20: description of operation ?display data write? *21: description of operation ?display on/off? end of initial settin g s end of data display function stabilization using command input (user settings) display data input direction select *17 function stabilization using command input (user settings) dis p la y on/off *21 function stabilization using command input (user settings) display data write *20 function stabilization using command input (user settings) page address set *18 function stabilization using command input (user settings) column address se t *19 fedl9445-02 ML9445 73/84 power supply off (*22) notes: sections to be referred to *22: the power supply of this lsi is switched off after switching off the internal power supply. function description ?power supply circuit? if the power supply of this lsi is switched off when the internal power supply is still on, since the state of supplying power to the built-in lcd drive circuits continues for a short duration, it may affect the display quality of the lcd panel. always follow the power supply switching off sequence. *23: description of operation ?power save? *24: description of operation ?discharge? a n y state function stabilization using command input (user settings) power save on *23 function stabilization using command input (user settings) discharge on *24 v dd -v ss power supply off when an external lcd power supply circuit is used external lcd power supply off fedl9445-02 ML9445 74/84 refresh although the ML9445 holds operation state by commands, excessive external noise might change the internal state. on a chip-mounting and system level, it is necessary to take countermeasures against preventing noise from occurring. it is recommended to use the refresh sequence periodically to control sudden noise. *25: regardless of presence of setting of ?read-modify-write? command, please carry out ?end? command. set to the state in which all commands have been set. test mode release command (e3(h)) refresh ram - display forward/reverse - set ?lcd all-on display? off - common output state select - display start line set - adc select - display duty set - n-line inversion drive register set - n-line inversion drive on/off - lcd bias set - voltage v1 adjustment internal resistance ratio set - electronic potentiometer - temperature gradient select - power control set - release the read-modify-write sate (end) (*25) - set ?nop? operation - display data input direction select - page address set - column address set - display data write - display on fedl9445-02 ML9445 75/84 mpu interface the ML9445 series ics can be connected directly to the 80-series and 68-series mpus. further, by using the serial interface, it is possible to operate the lsi with a minimum number of signal lines. in addition, it is possible to expand the display area by using the ML9445 series lsis in a multiple chip configuration. in this case, it is possible to select the individual lsi to be accessed using the chip select signals. ? 80-series mpu ? 68-series mpu ? serial interface v dd r eset v ss v cc gnd a0 a1 to a7 iorq db0 to db7 r d w r r es v dd v ss a0 c s1 cs2 db0 to db7 r d w r r es c86 p/ s decoder v dd r eset v ss v cc gnd a0 a1 to a15 vma db0 to db7 e r/ w r es v dd v ss a0 c s1 cs2 db0 to db7 e r/ w r es c86 p/ s decoder v dd r eset v ss v cc gnd port 5 port1 port2 r es v dd v ss a0 c s1 cs2 si scl r es c86 p/ s can be tied to either level. mpu ML9445 mpu ML9445 mpu ML9445 port 4 port 3 fedl9445-02 ML9445 76/84 pad configuration ML9445 pad layout chip size 12.7 x 1.26 mm chip thickness : 400 m 20 m 432 197 1 180 y x b a 433 196 448 181 (0,0) bump and alignment mark dimensions (pattern face) pad no.1 180 : 35 m 72 m pad no.181 196 : 84 m 30 m pad no.197 432 : 30 m 84 m pad no.433 448 : 84 m 30 m alignment marks a and b : see below [mark a] [mark b] alignment marks x-coordinate ( m) y-coordinate ( m) mark a 6215 -488 mark b -6228 508 aluminum (top metal) passivation 30 m 30 m 30 m 30 m 30 m 30 m aluminum (top metal) passivation 47 m 55 m 47 m 55 m coordinate position coordinate position fedl9445-02 ML9445 77/84 pad center coordinates pad number pad name x-coordinate ( m) y-coordinate ( m) pad number pad name x-coordinate ( m) y-coordinate ( m) 1 dummy -6059 -488 41 db6 -3193 -488 2 test1 -5979 -488 42 db6 -3133 -488 3 test1 -5919 -488 43 db7 -3001 -488 4 v ss -5839 -488 44 db7 -2941 -488 5 sdaack -5759 -488 45 vch -2838 -488 6 sdaack -5699 -488 46 vch -2778 -488 7 sync -5619 -488 47 vch -2718 -488 8 sync -5559 -488 48 svd2 -2615 -488 9 fr -5479 -488 49 svd2 -2555 -488 10 fr -5419 -488 50 test2 -2475 -488 11 cl -5339 -488 51 test2 -2415 -488 12 cl -5279 -488 52 v dd -2335 -488 13 dof -5199 -488 53 m/ s -2255 -488 14 dof -5139 -488 54 m/ s -2195 -488 15 cs1 -5059 -488 55 cls -2115 -488 16 cs1 -4999 -488 56 cls -2055 -488 17 cs2 -4919 -488 57 c86 -1975 -488 18 cs2 -4859 -488 58 c86 -1915 -488 19 res -4779 -488 59 p/ s -1835 -488 20 res -4719 -488 60 p/ s -1775 -488 21 a0 -4639 -488 61 irs -1695 -488 22 a0 -4579 -488 62 irs -1635 -488 23 v ss -4499 -488 63 test3 -1555 -488 24 wr -4419 -488 64 test3 -1495 -488 25 wr -4359 -488 65 v ss -1391 -488 26 rd -4279 -488 66 v ss -1331 -488 27 rd -4219 -488 67 v ss -1271 -488 28 v dd -4139 -488 68 v ss -1211 -488 29 db0 -4059 -488 69 v ss -1151 -488 30 db0 -3999 -488 70 v ss -1091 -488 31 db1 -3919 -488 71 v ss -1031 -488 32 db1 -3859 -488 72 v ss -971 -488 33 db2 -3779 -488 73 v ss -911 -488 34 db2 -3719 -488 74 v ss -851 -488 35 db3 -3639 -488 75 v dd -771 -488 36 db3 -3579 -488 76 v dd -711 -488 37 db4 -3499 -488 77 v dd -651 -488 38 db4 -3439 -488 78 v dd -591 -488 39 db5 -3359 -488 79 v dd -531 -488 40 db5 -3299 -488 80 v dd -471 -488 fedl9445-02 ML9445 78/84 pad number pad name x-coordinate ( m) y-coordinate ( m) pad number pad name x-coordinate ( m) y-coordinate ( m) 81 v dd -411 -488 126 vc6+ 2469 -488 82 v dd -351 -488 127 vc6+ 2529 -488 83 v in -271 -488 128 vc6+ 2589 -488 84 v in -211 -488 129 vc6+ 2649 -488 85 v in -151 -488 130 vc6+ 2709 -488 86 v in -91 -488 131 v out1 2789 -488 87 v in -31 -488 132 v out1 2849 -488 88 v in 29 -488 133 v out1 2909 -488 89 v in 89 -488 134 v out1 2969 -488 90 v in 149 -488 135 dummy 3049 -488 91 dummy 229 -488 136 dummy 3109 -488 92 vc3+ 309 -488 137 v h 3189 -488 93 vc3+ 369 -488 138 v h 3249 -488 94 vc3+ 429 -488 139 v h 3309 -488 95 vc3+ 489 -488 140 v h 3369 -488 96 vc3+ 549 -488 141 vs3- 3449 -488 97 vc5+ 629 -488 142 vs3- 3509 -488 98 vc5+ 689 -488 143 vs3- 3569 -488 99 vc5+ 749 -488 144 vs3- 3629 -488 100 vc5+ 809 -488 145 vc7+ 3709 -488 101 vc5+ 869 -488 146 vc7+ 3769 -488 102 vs1- 949 -488 147 vc7+ 3829 -488 103 vs1- 1009 -488 148 vc7+ 3889 -488 104 vs1- 1069 -488 149 v out2 3969 -488 105 vs1- 1129 -488 150 v out2 4029 -488 106 vs1- 1189 -488 151 v out2 4089 -488 107 vs1- 1249 -488 152 dummy 4169 -488 108 vs1- 1309 -488 153 dummy 4229 -488 109 vc2+ 1389 -488 154 vr 4309 -488 110 vc2+ 1449 -488 155 vr 4369 -488 111 vc2+ 1509 -488 156 v rs 4449 -488 112 vc2+ 1569 -488 157 v rs 4509 -488 113 vc2+ 1629 -488 158 dummy 4589 -488 114 vc4+ 1709 -488 159 v1 4669 -488 115 vc4+ 1769 -488 160 v1 4729 -488 116 vc4+ 1829 -488 161 v1 4789 -488 117 vc4+ 1889 -488 162 v1 4849 -488 118 vc4+ 1949 -488 163 v2 4929 -488 119 vs2- 2029 -488 164 v2 4989 -488 120 vs2- 2089 -488 165 v2 5049 -488 121 vs2- 2149 -488 166 v2 5109 -488 122 vs2- 2209 -488 167 v3 5189 -488 123 vs2- 2269 -488 168 v3 5249 -488 124 vs2- 2329 -488 169 v3 5309 -488 125 vs2- 2389 -488 170 v3 5369 -488 fedl9445-02 ML9445 79/84 pad number pad name x-coordinate ( m) y-coordinate ( m) pad number pad name x-coordinate ( m) y-coordinate ( m) 171 v4 5449 -488 216 com7 5075 495 172 v4 5509 -488 217 com6 5025 495 173 v4 5569 -488 218 com5 4975 495 174 v4 5629 -488 219 com4 4925 495 175 v5 5709 -488 220 com3 4875 495 176 v5 5769 -488 221 com2 4825 495 177 v5 5829 -488 222 com1 4775 495 178 v5 5889 -488 223 com0 4725 495 179 dummy 5969 -488 224 coms0 4675 495 180 dummy 6049 -488 225 seg0 4475 495 181 dummy 6215 -390 226 seg1 4425 495 182 dummy 6215 -340 227 seg2 4375 495 183 com31 6215 -290 228 seg3 4325 495 184 com30 6215 -240 229 seg4 4275 495 185 com29 6215 -190 230 seg5 4225 495 186 com28 6215 -140 231 seg6 4175 495 187 com27 6215 -90 232 seg7 4125 495 188 com26 6215 -40 233 seg8 4075 495 189 com25 6215 10 234 seg9 4025 495 190 com24 6215 60 235 seg10 3975 495 191 com23 6215 110 236 seg11 3925 495 192 com22 6215 160 237 seg12 3875 495 193 com21 6215 210 238 seg13 3825 495 194 dummy 6215 260 239 seg14 3775 495 195 dummy 6215 310 240 seg15 3725 495 196 dummy 6215 360 241 seg16 3675 495 197 dummy 6025 495 242 seg17 3625 495 198 dummy 5975 495 243 seg18 3575 495 199 dummy 5925 495 244 seg19 3525 495 200 dummy 5875 495 245 seg20 3475 495 201 dummy 5825 495 246 seg21 3425 495 202 dummy 5775 495 247 seg22 3375 495 203 com20 5725 495 248 seg23 3325 495 204 com19 5675 495 249 seg24 3275 495 205 com18 5625 495 250 seg25 3225 495 206 com17 5575 495 251 seg26 3175 495 207 com16 5525 495 252 seg27 3125 495 208 com15 5475 495 253 seg28 3075 495 209 com14 5425 495 254 seg29 3025 495 210 com13 5375 495 255 seg30 2975 495 211 com12 5325 495 256 seg31 2925 495 212 com11 5275 495 257 seg32 2875 495 213 com10 5225 495 258 seg33 2825 495 214 com9 5175 495 259 seg34 2775 495 215 com8 5125 495 260 seg35 2725 495 fedl9445-02 ML9445 80/84 pad number pad name x-coordinate ( m) y-coordinate ( m) pad number pad name x-coordinate ( m) y-coordinate ( m) 261 seg36 2675 495 306 seg81 425 495 262 seg37 2625 495 307 seg82 375 495 263 seg38 2575 495 308 seg83 325 495 264 seg39 2525 495 309 seg84 275 495 265 seg40 2475 495 310 seg85 225 495 266 seg41 2425 495 311 seg86 175 495 267 seg42 2375 495 312 seg87 125 495 268 seg43 2325 495 313 seg88 75 495 269 seg44 2275 495 314 seg89 25 495 270 seg45 2225 495 315 seg90 -25 495 271 seg46 2175 495 316 seg91 -75 495 272 seg47 2125 495 317 seg92 -125 495 273 seg48 2075 495 318 seg93 -175 495 274 seg49 2025 495 319 seg94 -225 495 275 seg50 1975 495 320 seg95 -275 495 276 seg51 1925 495 321 seg96 -325 495 277 seg52 1875 495 322 seg97 -375 495 278 seg53 1825 495 323 seg98 -425 495 279 seg54 1775 495 324 seg99 -475 495 280 seg55 1725 495 325 seg100 -525 495 281 seg56 1675 495 326 seg101 -575 495 282 seg57 1625 495 327 seg102 -625 495 283 seg58 1575 495 328 seg103 -675 495 284 seg59 1525 495 329 seg104 -725 495 285 seg60 1475 495 330 seg105 -775 495 286 seg61 1425 495 331 seg106 -825 495 287 seg62 1375 495 332 seg107 -875 495 288 seg63 1325 495 333 seg108 -925 495 289 seg64 1275 495 334 seg109 -975 495 290 seg65 1225 495 335 seg110 -1025 495 291 seg66 1175 495 336 seg111 -1075 495 292 seg67 1125 495 337 seg112 -1125 495 293 seg68 1075 495 338 seg113 -1175 495 294 seg69 1025 495 339 seg114 -1225 495 295 seg70 975 495 340 seg115 -1275 495 296 seg71 925 495 341 seg116 -1325 495 297 seg72 875 495 342 seg117 -1375 495 298 seg73 825 495 343 seg118 -1425 495 299 seg74 775 495 344 seg119 -1475 495 300 seg75 725 495 345 seg120 -1525 495 301 seg76 675 495 346 seg121 -1575 495 302 seg77 625 495 347 seg122 -1625 495 303 seg78 575 495 348 seg123 -1675 495 304 seg79 525 495 349 seg124 -1725 495 305 seg80 475 495 350 seg125 -1775 495 fedl9445-02 ML9445 81/84 pad number pad name x-coordinate ( m) y-coordinate ( m) pad number pad name x-coordinate ( m) y-coordinate ( m) 351 seg126 -1825 495 396 seg171 -4075 495 352 seg127 -1875 495 397 seg172 -4125 495 353 seg128 -1925 495 398 seg173 -4175 495 354 seg129 -1975 495 399 seg174 -4225 495 355 seg130 -2025 495 400 seg175 -4275 495 356 seg131 -2075 495 401 seg176 -4325 495 357 seg132 -2125 495 402 seg177 -4375 495 358 seg133 -2175 495 403 seg178 -4425 495 359 seg134 -2225 495 404 seg179 -4475 495 360 seg135 -2275 495 405 com32 -4675 495 361 seg136 -2325 495 406 com33 -4725 495 362 seg137 -2375 495 407 com34 -4775 495 363 seg138 -2425 495 408 com35 -4825 495 364 seg139 -2475 495 409 com36 -4875 495 365 seg140 -2525 495 410 com37 -4925 495 366 seg141 -2575 495 411 com38 -4975 495 367 seg142 -2625 495 412 com39 -5025 495 368 seg143 -2675 495 413 com40 -5075 495 369 seg144 -2725 495 414 com41 -5125 495 370 seg145 -2775 495 415 com42 -5175 495 371 seg146 -2825 495 416 com43 -5225 495 372 seg147 -2875 495 417 com44 -5275 495 373 seg148 -2925 495 418 com45 -5325 495 374 seg149 -2975 495 419 com46 -5375 495 375 seg150 -3025 495 420 com47 -5425 495 376 seg151 -3075 495 421 com48 -5475 495 377 seg152 -3125 495 422 com49 -5525 495 378 seg153 -3175 495 423 com50 -5575 495 379 seg154 -3225 495 424 com51 -5625 495 380 seg155 -3275 495 425 com52 -5675 495 381 seg156 -3325 495 426 com53 -5725 495 382 seg157 -3375 495 427 dummy -5775 495 383 seg158 -3425 495 428 dummy -5825 495 384 seg159 -3475 495 429 dummy -5875 495 385 seg160 -3525 495 430 dummy -5925 495 386 seg161 -3575 495 431 dummy -5975 495 387 seg162 -3625 495 432 dummy -6025 495 388 seg163 -3675 495 433 dummy -6215 360 389 seg164 -3725 495 434 dummy -6215 310 390 seg165 -3775 495 435 dummy -6215 260 391 seg166 -3825 495 436 com54 -6215 210 392 seg167 -3875 495 437 com55 -6215 160 393 seg168 -3925 495 438 com56 -6215 110 394 seg169 -3975 495 439 com57 -6215 60 395 seg170 -4025 495 440 com58 -6215 10 fedl9445-02 ML9445 82/84 pad number pad name x-coordinate ( m) y-coordinate ( m) pad number pad name x-coordinate ( m) y-coordinate ( m) 441 com59 -6215 -40 442 com60 -6215 -90 443 com61 -6215 -140 444 com62 -6215 -190 445 com63 -6215 -240 446 coms1 -6215 -290 447 dummy -6215 -340 448 dummy -6215 -390 fedl9445-02 ML9445 83/84 revision history page document no. date previous edition current edition description fedl9445-01 apr 27, 2012 ? ? final edition 1 3 3 add v1 (v bi ) 5 5 add explanation of *6 19 19 v rs test pins output pins 33 33 to 35 add explanation of power supply circuit 34 36 to 37 add explanation of 1 st voltage multiplier circuits 35 38 add explanation of 2 nd voltage multiplier circuits 41 to 42 44 to 49 add explanation of application circuits pedl9445-02 dec 20 ,2013 - 50 add cascade connection example fedl9445-02 ML9445 84/84 notice no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants an d any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation eq uipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the pr oducts safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semi conductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed sc ope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2013 lapis semiconductor co., ltd. |
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